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Re: pad design
Hi
Thanks for your reply. This is not for a bond pad as i have mentioned we are not packaging. This is a regular probing pad, we will be using our own test equipment to do the measurements. I basically wanted to know whether i should construct a metal skyscraper or do i simply...
Hello
i am working on a test-chip using ibm-soi 45nm design kit provided by MOSIS. We are not packaging our die. Currently i am working on making the pads. I have decided on making them 100 x 100 micron sq since that will ensure sufficient landing area for any type of probe we use (ac or dc). I...
Re: Probe-pad design
Actually both. I think i can figure out how much capacitive load those pads need to drive & have buffers accordingly. But what i am more concerned about is the actual pad. Is is supposed to be like a giant metal block with contacts? with/without glass layer?
Hello
I am using the 45nm IBM-SOI toolkit of MOSIS to do my custom design. I wont be packaging my die and hence will be just using metal-pads. I will be appreciate it if any of the experienced designers over here can provide some insight on how to go about pad-design. I can understand these...
Hello
I am using the 45nm IBM-SOI toolkit provided by MOSIS for my custom design with Cadence Virtuoso. Right now i am working on the layouts of my design. I am using the Calibre tool-suite for DRC/LVS/extraction.
For a simple inverter although my design is DRC clean when i try to run an LVS i...
Hello All
I am starting with the layout of my system using 45nm IBM-SOI models provided by MOSIS. I am using Calibre to do DRC/LVS & using the rule-decks provided by IBM. For the simple inverter i am consistently getting the following 2 errors. All other errors can be eliminated by judiciously...
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