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Recent content by bb12mpc

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    Any method to verify 8051-1T is really running at 1 ck/instr

    8051 1t Does anyone know any quick and easy method to verify a 8051-1T is really running at 1T performance, i.e. 1 clock per instruction cycle? I am going to purchase a 8051-1T soft core and need to plan how to "prove" the performance of it. Any input would be highly appreciated. Thanks, Mark
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    Source Verilog examples on implementation of Enhanced UART

    Enhanced UART I am now converting a standard UART to "enhanced" UART which has new features of fram error correction, multiple slave hook up... Can anyone share any example of source verilog on this implementation? Thanks!
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    Verilog examples of how to implement a master/slave SPI

    Master/Slave SPI Is there any example or source verilog for how to implement a master/slave SPI? Thanks!
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    Need design specifications of Verilog code of 8051 PCA

    Does anyone has detailed design spec or verilog code of 8051 PCA module to share? Thanks, Mark
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    CMOS high-to-low level shifter: how it works?

    Dear maxwellequ, Thanks for the prompte response. But what I saw from the schmatic of my high-to-low level shifter, the first and second inverters' VDDs are both connecting to the low-v supply. So, is it wrong on the ciruit? Or the different transistor sizes do the trick? Thanks, Mark
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    CMOS high-to-low level shifter: how it works?

    Dear all, I am doing to a multi-vdd SoC design, there is a high-to-low level shifter available in the process. What I understood on high-to-low shifter is to aviod over-stressing from high-v output to low-v input (pls correct me if I am wrong!). When I look at the circuit, the high-to-low...
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    8051 CPU Core Bus Timing Model

    Dear all, Is there any existing bus timing model to 8051 CPU Core (not the 8051 chip bus timing!!)? Such as, bus timing model for SFR bus, XDATA bus,... I am looking for a bus model such that I can develop a custom module that going to hook up to the internal bus, e.g. SFR bus, with 8051 core...
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    oc8051 simulation doesn't work?

    Dear all, Can anyone sucessfully simulate oc8051 (downloaded from www.opencores.org)? I got simulation failure for all pattern come with the package. Any input would be highly appreciated. Thanks, Mark
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