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i used 2 uart different codes...
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity my_rX is
port ( rst,clk : in bit;
data_out : out bit_vector ( 7 downto 0);
rx_ser_in...
hi all
i wrote a vhdl code for uart receiver, but i cant get the 9600 bps with my Altera kit.
i use Altera cycloneII FPGA development kit [EP2C20F484C7N].
there is 3 kind of clocks 24Mhz, 27MHz and 50MHz.
my uart code use counter that count a clocks and every 16 ticks its one bit.
thats mean i...
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