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I managed to solve the issue:
1. Firstly, I made the capacitor (m=60) as a separate component and removed it from A. I then brought the capacitor in D. This resulted in LVS having two errors instead of 60 for the capacitor.
2. The two MIMcaps that were the problem at this point were placed above...
UPDATE:
I have been analysing the issue and found the possible culprit: I have a subcomponent of A that includes a MIMcap with a multiplier of 60. The LVS of this subcomponent is correct, but the LVS includes a list of "Ambiguity Resolution Points", all of which are these MIMcaps. This is...
Hi,
I have a really weird issue with the layout of my design (TSMC 0.18um BCD). I have three components (A, B and C), all of which are LVS and DRC clean and sitting in their own respectable NBL. Component A has a large MIMcap (multiplier 60) with a 1.8V, 5 V, floating 5V and HV inputs, B is a...
Hi all,
I am looking for a unity gain buffer to buffer analogue signals out of the chip for testing. I need it to operate at least up to 40 MHz and drive Cl = 25 pF with small distortion. I am using 1.8 V devices from TSMC 180nm PDK, but the supply voltage is 1.3 V. Current consumptions does...
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