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Yes, indeed I'm going through Europractice MPW... but I think the docs from AMS should cover also mini-ASIC runs, so this information should in any case be there! Oh well... waiting for Europractice and AMS e-mail replies ;)
Hey Erik, I was thinking the same (that DRC rules were not enough), that's why I posted the question here. Anyway, it is VERY strange that AMS does not provide this info in their docs... they have a very similar pic to the one you posted, but without values for the min. circuit distance!
I...
Hi Leo,
Thanks for the help. On the design docs, the seal ring is described as the "SCRIBE" cell, so, although I was wrong on the terminology, we are talking about the same thing. However, the document does not seem to indicate any rule for distance between the seal ring and my circuit, maybe...
Hi, I'm finishing a design on AMS H35B4 tech, but my chip does not have PADs on all sides...
I'm not sure if I indeed need to put the scribe line on my design, of if just the min. width MET1 path is enough... in any case, my real question is: what is the minimum distance I should put my circuit...
Did you ever find out what were these instances, in special SDW2?
I have two nmos in my layout, that calibre is grouping in this SDW2, and I think that this may be the cause of the LVS error...
Hi Keith, my application indeed is for photodiode amplifiers...
I've just started reading this book:
Photodiode amplifiers : op amp solutions / Jerald G. Graeme. - New York [u.a.] : McGraw Hill, 1996
which will hopefully help me understand all the issues in the design of the TIA.
Currently...
Hi guys, once more, thank-you for your help!
It's been some time since you have replied, but it's not that I'm not interested in this, it is only that unfortunately my weekdays have been crazy ehehe...
Anyway,
I think I understood when LvW said that the infinite input impedance is allowing...
Hey keith, thank-you for your reply, but are you sure this will happen?
I was doing some very simple math here, and what I got was:
Supposing a Op-Amp with gain A, infinite input impedance and zero output impedance, we would have that:
Vout = -Vin*A (negative feedback, positive input of...
Hi guys,
I've been playing around with the design of a high-gain high-BW transimpedance amplifier (TIA).
I've read again and again the theory behind all this but I have a question that maybe is a bit stupid, but...
What happens if I try to set the TIA gain higher than the DC gain of the...
Hi everyone, I got a new setup for L-Edit from Fraunhofer and now the POLY2 capacitance seems to be less than 1fF. The POLY1 also dropped to like half of what it was.
Thanks for all the help,
Leo.
Ken,
As Masteric said, you cannot get the total device mismatch from simulations. The mismatch must be defined by the foundry, normally in the Process Parameters document or Mismatch parameters.
With these foundry supplied parameters, you fill in the variation block that I talked about before...
Ken,
To simulate mismatch in all devices of the circuit I normally use the DCmatch analysis of HSpice. I've been designing a D/A myself and this analysis has helped me very much to evaluate the mismatch in my circuit.
In HSpice, the mismatch is defined in a block in the netlist called...
Hi everybody,
I've been trying to do a DCmatch analysis in a R-2R circuit with transistors as the resistive devices. The R-2R circuit is functioning as a D/A converter with current output. Each branch of the R-2R has a switch connecting it to the output or to the ground. These switches are...
reason of how parasitic capacitance
Hi Erikl... I thought about that too... but I couldn't see how this would be logical for the extractor to do... My capacitor is connected between two nodes of my circuit, and not to ground. The parasitic capacitances always connect from one of the nodes...
pip capacitor
Hi everybody...
I've been doing some layout of analog circuits in AMS 0.35 CMOS process. I use Tanner Tools as layout editor, and I'm seeing some strange behavior when extracting the layout with parasitic capacitances.
For instance, if I try to extract just the layout of a...
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