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Recent content by banihashemi

  1. B

    Ground connection in Mixed signal IC design

    if you have enough pins the best performance is connecting each A,B,C and D outside the chip together.
  2. B

    ADC dynamic parameters test

    it is true to reduce the amplitute to 90% full scale.
  3. B

    function of the capacitance

    the impedance of the follower load decreases at high frequencies.
  4. B

    About CMOS signal path

    for a certain bias current and to have a certain (vgs-vt) PMOS transistor width should be more than 3 times NMOS that causes 3 times more parasitic capacitance
  5. B

    about step change in the output of SC circuits

    A good book is "Analog MOS integrated Circuits for Signal Processing" by Gabor C. Temes
  6. B

    Intel's "2000 packaging databook" (chapter on ESD)

    Re: esd For a constant charge, low capacitance results in a high voltage.
  7. B

    fringe capacitance calculation

    capacitance calculation fringe Fringe capacitance depends on the layer. For metals, upper layers are thiker and so there is more fringe capacitance between two upper metal layers with the same kind.
  8. B

    commom centroid geomentry

    it is used for matching purpose for any alements in an IC. because mismatch is due to different things that the most important of them is ingrediants.
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