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    high-gain high-BW op design

    Hello guys! Is there any op design/architecture such that it can have a gain of at least 65dB at 500MHz? I am using TSMC 0.18um CMOS process. My load capacitance is about 10fF (the gate capacitance of a MOS transistor). I tried a folded-cascode op, having a bias current of 350uA. With this...

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