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I don't understand about your question clearly.
But in subthreshold region for a mos, we can get
Id = Io EXP[Vgs/(ζ*Vt)] k is a constant number
gm=δ(Id)/δ(Vgs) = Id/(ζ*Vt)
Av = gm*ro ≈Id/(ζ*Vt) * 1/(λ*Id*k) => Av is indepedent of Id
So if in your question, the condition is like...
I am a newer designer in SCF.
I design a second-order post filter in delta-sigm DAC.
I can get the ratio of Cin and Cfb in each stage SCF to meet the transfer function.
But I am confused about how to determine the real size of Cin
As I know, the thermal noise of first op amp input pair and...
Deat All,
Can anyone give me any comment about the short-circuit detection and protection circuit used in PowerMOS?
My operated current is 50mA for normal and 250mA for short-circuit .
Thanks a lot.
Hi Robertt,
First, I think you point out one thing. A signal inculde DC part and ACpart. So you may divid an input signal into two parts : CM level and differential level.
When you design an OP , it's used to amp the small signal vary on the CM level. So when you calculate the...
Hi Robertt,
You said you may understand
Vout1,2(min) = Vin,CM-Vth,n (Why use Vin,CM ?)
But you can't understand
Vout1,2(max) = Vdd - (|Vsg3|-|Vthp|)
When you use Vin,CM , Id =Iss/2 ?
Is it right? Why?
unstable bandgap
Hi Btrend,
Can you explain how the op work in whole loop to make sure vip = vin ? And you can simulate the loop gain and phase margin in whole loop to see if it's really stable. Maybe it will be helpful for you.
non-integer divider
Dear All,
Thanks all response.
My target is the frequency divider using normal
logical circuit . In actually, I had got the divider circuit
with divisor 2.5. But I am interesting about how to
analysis or design the non-integer divider by myself.
non-integer divider
Dear All,
If anyone can give any idea about how to design a non-integer divider quickly?
Such as divider with divisor 2.5 , Thanks a lot
Dear Jake,
Based on the paper ,
Vbg= Vbe2+N(R2/R1)ln[M(N+1)]*Vt
In your circuit R2/R1=7.4 , N=1 .
So you should let M to be about 16 in order to get the zero temperature coefficient.
when Vbe2 has temp coefficient -2.2mV/C and Vt has +0.085mV/C
because I didn't see the ratio of bipolar in...
jake,
As Btrend asid, I think you should check if VN1=VN3
in your circuit. And in your circuit, NPM-1 and NPM-2 have the same w/l ratio ,but one is marked as 30uA and the other maked 2.5 uA ? It 's not resonable for me.
12 to 5v regulator
Thank your response.
And If we need to design the circuit integrated to chip
can we use the normal process like TSMC 0.25um process ? Or we need a special process ?
Because th input voltage can vary from 7V to 40V .
12v to 5v regulator
Dear all,
If someone can give me any suggestion about how to start in design a 12V to 5V regulator design (output current : 300mA max)?
My boss give me the topic , but I don't have any idea in this region .
So can you give any comment to design this...
pwm dac
Hello,
If anyone can explain what's the different between the PWM DAC and
Delta-Sigma DAC?
If they can be used in the same purpose of audio? They tell us PWM
DAC can use pure logic process and Delta-Sigma DAC need mixed signal
process .
Thanks in advance.
I got some information from engineer from TSMC.
In area consideration, the area of unit cap between
MiM and 1p5M sandwhich cap is close. But in the
accuracy consideration, MiM is much better than
sandwhich cap. So if we need high accuracy system,
we should use the MiM Process.
Hi all,
Can anyone give me value/um^2 about the double poly cap and sandwhich cap(five metal and one poly) in 0.35um or 0.25um TSMC
process. Because I don't have the document on my hand.
And what's the consideration in selection between them, such as
area, noise etc, when design analog...
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