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Recent content by bachoo786

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    Read from a text file

    Hello there, I have got this code for reading data from a text file into a RAM. I get this warning "net mem [0][7] does not have a driver." Can anyone please have a look at my code, if I am missing something? Many thanks !! library ieee; use ieee.std_logic_1164.all; use...
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    FOR LOOP in testbench

    Yes I have posted a ROM and I need help writing a testbench using a FOR loop. I find it difficult due to the text file approach in my ROM. Can you please help show me the test bench with a FOR loop that has a text file implemented in a ROM? Many thanks!!
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    FOR LOOP in testbench

    Hello there, I needed help with test bench. I am using a FOR loop for my test bench to evaluate values that are stored in a text file inside a LUT. Here’s my VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use STD.TEXTIO.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL...
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    VHDL Fixed point representation and for loop

    anyone?????
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    VHDL Fixed point representation and for loop

    I am now running a testbench with FOR Loop and I need your help. I get errors and I tried to rectify them with no luck. Here's my code, can someone shed some light please? ------------------------------------------------------------ -- VHDL Testbench for rom_ent -- 2013 2 2 12 40 1 -- Created...
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    VHDL Fixed point representation and for loop

    well it works with altium designer and gives me no errors?! - - - Updated - - - I would still need a text file for my second operand as it’s not a constant! Also I am asked to use pre calculated values from matlab.
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    VHDL Fixed point representation and for loop

    Oh right...well I introduced an init function, here's my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use STD.TEXTIO.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; Entity ROM_ent is Port( ADDR: IN std_logic_VECTOR(7 downto 0); CLK: IN std_logic; DATA: OUT...
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    VHDL Fixed point representation and for loop

    I managed to get a code for initialising my generated values to the addresses in the LUT but I get the following errors: -syntax error near for -i is not declared -synax error near loop -unit behavioural ignored due to previous errors I tried to resolve these errors but had no luck so far, I...
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    VHDL Fixed point representation and for loop

    Thanks for the reply TrickyDicky. I will use that approach for the first operand, but for my second operand i.e. log2(mantissa), I don’t have any constant and therefore I would need to initialise my values from a text file. So I still need a bit of help with the coding. Can anyone help me...
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    VHDL Fixed point representation and for loop

    Thanks guys for all your inputs ! I did manage to generate values for my LUT by using base 2 instead of 10 and got whole numbers for my first operand i.e. (exp*log(2)). I have stored these values on a text file and I now need to assign them to individual addresses on my LUT i.e. 256 addresses...
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    VHDL Fixed point representation and for loop

    anyone????
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    VHDL Fixed point representation and for loop

    Right, I had truncated my values to tell you the truth and its true that I had no resolution. Basically, I am doing logarithm of a floating point number, single precision to start with. The general equation when you apply logarithm to a floating point number is exp * log(2) + log(mantissa). I...
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    VHDL Fixed point representation and for loop

    As in what I meant was, if a=(log(2) * exponent) than a will be having 256 different values as the exponent varies from 0 to 255..and the log(2) is constant. So for example when exponent is 1 than a=0.3010299957 this value needs to be represented in 8 bits I.e. 0.01001101000... Hence if you...
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    VHDL Fixed point representation and for loop

    Hello smart people :) I needed guidance on representing fixed point numbers on vhdl. I will present the problem: exponent * log (2) where exponent= 2^8 and (log (2)) is constant. I need to represent the values of the above equation in vhdl (256 entries) using 8 bits only. I am not allowed to...
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    FPGA-based floating-point logarithm unit

    Right so I forgot to mention but I am new to VHDL and maybe that is why we are not on the same wavelength. Fair to say what you explained me above but may I ask you one thing: after writing down the VHDL code for the LUT for (exp*log2) what’s the next step? as in how do you perform the...
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