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Hi all,
According to my understating, all procedural blocks are running in parallel.
Please have a look at this simple verilog code. This is generating a clock and works fine.
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module test;
reg clk;
initial begin...
Re: modelsim (installation tutorial at www.vlsi-world.com)
hi check this link. it is usefull for you at www.vlsi-world.com
**broken link removed**
have fun
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