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Hi erikl,
I am very very very thank you for your reply, also, I have tried the command advised.
The code shows as below:
/*----------------------------------------------------------
.param VGS_m4 = 'abs(v1(mpm4) - v2(mpm4))'
.param VGD_m4 = 'abs(v1(mpm4) - v3(mpm4))'
.param VGB_m4 =...
Dear all,
I want to use HSPICE to figer out whether the MOSFETs in a schematic have been over-drived.
For example, if the VGS, VDS or VGD of a 1.2V mos run up to 1.32V/-1.32V, it is desired that hspice could generate a report about it.
Anyone knows which command can be used to...
As follows, fig1 shows in the tag, there is a limiter after dickson charge pump, to limit the supply.
Fig2, can we assume the limiter as some diodes? It means that, if the limiter do work, we can regard it as a small resistor which in parallel with the system, thus the voltage of the system is...
In this circuit, IN is common voltage, and the differential signal input through IP
the res fix the coefficient of feedback, now, if i change the value of the res (but not change the proportion), the frequence response will change.
if the value increases, the BW becomes narrower and phase margin...
For the DC analysis, if Vcm-n and Vcm-p of the amplifier is different, the cancellation circuit will adjust them to equal by detecting the difference between Out-n and Out-p.
But for a differential signal, it also leads to a difference at the output, won't the feedback also change the input?
It...
Re: N-well (NW) and N-well for high voltage (NWH) in smic18pf
But, if there is a break down, where it is? Because VDD is high, so the operational environment of the PMOS is ensured. If the gate is low, source is high, body is high, how could my drain become low, it makes us confused.
Maybe...
Uhh...I made a mistake there...and the details are updated above
---------- Post added at 13:11 ---------- Previous post was at 12:59 ----------
Mm..hmm...
In a layout, I put both NW and NWH over a 5V PMOS, as follows
Could someone please tell me what it affects?THX
The circuit shown as follows, in the test, if the IN is high, the output is high, but if the INis low, the output turns to high from low afer 58ms, and there are signs that a large...
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