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Hi all,
I'm designing an asynchronous fifo with read freq=66Mhz and Write freq of 166 Mhz, with no information about data burst or data rates.
How Could i calculate the Fifo's depth ? is there any suggested size in this case ?? or it will be infinite ??
Thanks,
Ayman
I have seen that and also i have searched Wikipedia and another websites but also i have a problem in designing a block diagram for the SPDIF Rx. i need to spec this Rx as we are working in an HDMI 2.0 project so we need that interface.
i found:
**broken link removed**...
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