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Recent content by Ayman Essam

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    Delta-Sigma ADC FFT peaks

    hi thank you for your help regarding what you say " But best is you use an input frequency that is a pure integer multiple of 1/81.29 ms = 12.3016 Hz and is derived from the same clock source as the sampling clock." do i have to chose prime odd number ? odd? even ? any integer ?
  2. A

    Delta-Sigma ADC FFT peaks

    Hi i designed a Delta sigma ADC ( switch-cap), with the FFT plot attached, the issue is i don't understand why such peaks exist (my Fin = 3.3 Khz, my Sampling Freq = 100KHz)
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    switch-cap integrator's output is so high,

    I am using switch-cap circuit
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    switch-cap integrator's output is so high,

    Hi my opamp's open loop gain is above 60 dB's, and the In/out common-mode voltages are stable in the mid-scale of VDD, but the output differential of the integrator is very close to VDD !!! any help with that ?
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    bandgap is not working with corner (BLOW, Chi, Rhi, Tsf, high supply, high temperatu

    Hi i designed a bandgap, and across all PVT corners everything looks ok, except the corner mentioned above, i loose all the Av, PSR, PM and everything!!!! any help ? Dankuwel
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    Bandgap start-up at low temperature

    Thank you for your reply, but I hardly understand your tracing methodology, would you please elaborate a bit more?
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    Bandgap start-up at low temperature

    Hi I've designed the BGR with Core OTA works with high gain, high phase margin, and high PSR. When I transient-test the BGR, at LOW TEMPERATURE, the BGR doesn't give the output voltage. Any help about it ?
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    Bandgap Reference's OPAMP PVT-stable DC bias point

    Hi I am designed a self-biased Folded-Cascode OpAmp for a Bandgap reference, and the main issue is that no clear DC bias point that can fully operate the Design at its best performance at all PVT corners, especially the supply and the temperature as they change mobility and Vth alot !! I need...
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    What is the main difference between CIFB and CIFF delta-sigma modulators ?

    I am really confused about the main differences. any help will be appreciated
  10. A

    Switched Capacitor Integrator Output Common-Mode Level

    Hi I am designing a SC integrator as shown in the schematic attached. The problem is that the output Common-Mode Level is not stable ... i mean it gives me always VDD "1.2V". I'd really appreciate your help.
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    Measuring Switch-Capacitor OpAmp specifications

    Hi, I'd like to know how to measure the Gain, BW, Stability, etcc with Cadence Virtuoso, for an Opamp integrator with switch capacitor circuitry ?
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    Cadence Virtuoso 6.1.5 isn't showing transistor Region

    Hi I am trying to display the MOSFET operating region by selecting edit-> component display .. and all what I can have is this in the attached image. It has no "Region" please help Thx !!
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    opamps polarity in boosted output impeadance

    hi how to choose the opamps polarity in the two single-stage topologies attached
  14. A

    ultra-low-power analog IC

    in a paper https://www.mdpi.com/2079-9268/6/2/10 what is meant by sub-Vt saturation region ? i know it isn't the normal saturation region where VDS>VGS-VTH. does the above expression mean its the maximum current that can be drawn in the sub-Vt domain ?
  15. A

    Sigma Delta Analog to digital calibration

    Hi, I need a book or reference that discusses the ADC's Calibration .... what is it ? and why is it done ? and how ? and does it differ from an ADC type to another ? Thxx
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