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Re: What is the replacement of function "Reconnect" of OrCAD Layout in PCB Editor.
What version of PCB Editor you use? Can you show screenshot of an about window?
Eagle is not comparable with Allegro. But maybe it has exactly this feature.
But i think that netlist is better in any case. Normal...
Re: What is the replacement of function "Reconnect" of OrCAD Layout in PCB Editor.
Yes, of course, these options are in Logic menu, not in preferences. If you don't see it try to change product via File-Change Editor... Maybe this helps...
Re: What is the replacement of function "Reconnect" of OrCAD Layout in PCB Editor.
Ok, now i understood. PCB Editor is bad choice for such things. It works with netlist and is good for big projects and not for drawing from scratch. But you can, if you want.
First, go to preferences and verify...
Re: What is the replacement of function "Reconnect" of OrCAD Layout in PCB Editor.
I have no expirience in Orcad Layout and not sure that i fully understand this function.
But you can make new connections even from blank spaces and pins, not only pins with assigned nets. If you don't have a...
Re: What is the replacement of function "Reconnect" of OrCAD Layout in PCB Editor.
Connections are generally defind by netlist. You must creae schematic and forward annotate it to PCB.
You can also change net connectivity by selecting Net Logic from Logic Menu.
Changes are done in options pane...
1. Go to the menu View-Windows and make sure that checkbox for Options is checked.
2. When placing pins use browse buttons on the options page (located usually on right side) to select padstack.
3. Search path for padstacks is determined by padpath variable (serach for word "padpath" in...
It is placed when you include it into silkscreen gerber file. Verify your gerber before sending it to manufacturer by opening it in a viewer like CAM350 or by importig it back into Editor.
If you dont' see any refdes then go to manufacturing-artwork and edit particular silkscreen gerber by...
Stackup is correct but i advice you to control impedances.
Try to route most hi-speed traces on top. For correct termination read appnotes for both SDRAM and controller.
Look here.
Or here.
There are many others.
Don't worry about interwire clearances until your voltages are not in kV range. Use usual interwire clearances inherited from your main design rules and based on manufacturers possibilities.
What are examples of such speedy interfaces? I don't know it. I'm not familiar with modern 40G-100G technology but i estimate that all this speed is divided into one or more lanes like in PCI Express. Real speed is then much slower.
At so high frequencies we can't do any srepentines because any...
Again, as i said above, if you place parts including caps on top you get the best result including routing space. Placing caps on bottom is needed only in case of BGAs, where you can't connect a power pin with directly to cap pin. Such placement lead to greather inductance in current path. Here...
Place all of your powers on one pwr layer to keep ground undisturbed. If you plan to place more parts on top then choose TOP-VCC-GND-BOTTOM. That is because you can't route good in top: components are on top. Route your signals mainly on bottom. Then you have good reference for bottom's...
Right. In 4-layer board you can made power and ground layers. This is very good for power integrity. Good power means stability also in high frequency operations. Also having gnd plane is better for impedance control because manufacturers need a reference plane to do impedance measurements in...
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