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Recent content by awais107

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    Synopsys IC Compiler Macro/SRAM issue

    Integrating Synopsys SRAM_1KB in the design (ICC issue) Hi I want to integrate synopsys SRAM_1KB blocks in my design. I synthesized my code without SRAM using design compiler and than later on combined with synopsys SRAM_1KB. But now when i use this as combined version as top module to...
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    Integrating Synopsys SRAM_1KB in the design (ICC issue)

    Hi I want to integrate synopsys SRAM_1KB blocks in my design. I synthesized my code without SRAM using design compiler and than later on combined with synopsys SRAM_1KB. But now when i use this as combined version as top module to icc (for place and route), it gave me error. That module...
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    Cadence Virtuoso AMS (IC 6.1.5)

    Hi I need some tutorial regarding cadence virtuoso AMS simulation for version IC 6.1.5 or any 6.X version. Thanks,
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    How to run AMS simulation in Virtuoso?

    Hi Were you able to find some useful brief tutorial? If yes do share with me, I am also looking for digital + analogue co-simulation. Thanks
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    Creating schematic from Verilog in cadence

    I want to first verify the behavioral level working in the virtuoso. Can i do that ? Without synthesizing. I tried to make a schematic symbol of verilog code (behavioral level) and was still getting the same error. - - - Updated - - - Thanks. But do you have any idea of converting verilog...
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    Creating schematic from Verilog in cadence

    Thanks. But after synthesize how can i make symbol and link with my schematic. (how to call it in the virtuoso) Also, is there any way to verify the behavioral working in virtuoso using ADE-XL from verilog code Thanks - - - Updated - - - I tried to add the synthesize version but still...
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    Creating schematic from Verilog in cadence

    Hi I want to create schematic of a verilog file in cadence. My goal is to simulate verilog file in cadence ADE-XL using ADC and DAC. But, when i make a verilog file (of simple 8 bit adder) and its symbol in cadence, its netlist don't get generated at simulation level and i get an error.
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    Digital Leaky Integrator (First order IIR digital LPF)

    Can you elaborate how the cut-off frequency of 0.01Hz has time constant of 16Hz. If you can share the mathematical background regarding and how to calculate it.
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    Digital Leaky Integrator (First order IIR digital LPF)

    Thanks. Also, one another thing. Normally in digital leaky integrator what is the settling time for lets say 0.01Hz cut-off frequency. As, in analogue implementation the settling time will be very high for the similar specifications.
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    Digital Leaky Integrator (First order IIR digital LPF)

    Hi I need some guidance regarding the implementation of Digital Leaky Integrator (First order IIR digital LPF) using full custom flow. I implemented the following: https://www.physi.uni-heidelberg.de/~angelov/VHDL/VHDL_SS09_Teil06.pdf (slide 32) Attached (Doc4.docx ) But the simulation in...
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    Selecting Clocks and Number of Bits in OFDM

    Hello, I want to implement and OFDM transceiver chip and my question is how to select the clock frequency of IFFT block? the number of output bits of IFFT block? Also, for the DAC how to select the clock frequency and the number of output bits? Need urgent help...plz Thank you
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