Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have already used -instance as shown in the following read_saif command.........
read_saif -input waves.saif -instance test_tb/dut -rtl_direct
I have not used the -target argument . I am not sure how to use the -target argument. I could not find anything online how to use that.
- - - Updated...
Thank you for reply. I understand that since Modelsim is a simulator the test bench should be the top module whereas since the DC is a synthesis tool, the circuit should be top module. But if this is the error then how can I overcome this.
I am trying to generate power report using Synopsys DC compiler.
At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command.
Then I proceeded to analyze the power through DC compiler.
However, I am getting an warning " There are...
What is meant by acquisition range of PLL?
How does it depend on loop bandwidth?
When we work on discrete PLL domain, how does it affect the acquisition range?
I am currently working on timing recovery design of digital receiver. One of the specification is given as Acquisition range should be...
Hi!
I am trying to design the Symbol timing recovery(#STR) block of #DVBS Receiver. For reference, I am using the following matlab simulink design (NDA timing recovery part within Digital Baseband Receiver)
**broken link removed**...
The design has considered a roll-off factor of 0.5. I...
For complex RTL designs with multiple conditions, use of assign statements can be very hard to work with ( for example you have to use multiple "?" conditional operator making the code hard to read. So you can always always@(*) to design the combinational part of the circuit where you can use...
please help me with the information that whether MIPS and RISCV are copyright protected or not. So if not whether one can go for full ASIC tapeout of SOC developed from RISCV/MIPS cores with various peripherals.
I have installed ELECTRIC vlsi deisgn system in linux. Now how can I proceed to do simulations of circuits and layouts in electric. please guide me what plugins to install and how to install for performing circuit level simulations.Thanx in advance.
is it possible to use parametric analysis in cadence verilog-ams............for example there is a parameter w defined by the verilog-ams model by me..........no i want to do parametric analysis by changing w through a certain range and plot a function(y with respect to x) for different values...
i have designed a static RAM circuit(32 nm). I wanted to perform simulation for read operation. So i needed to set the bit lines to vdd(0.9v). I used nodeset command to set the initial volatge of bitline to vdd, but the initial voltages remain upto 0.35 volt. So can u tell me what is going wrong...
i am designing a nand, nor, etc logic circuits(mosfet) using cadence @ 32nm technology.what should be the appropriate capacitive load that i have to use corresponding to fan out of 1?..............please give some links to read about this
how can i know what does the different parameters in the gpdk180 file means. for example there are different parameters are given in nmos1.scs file with their values...but how can i know which parameter denotes what?..............
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.