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Recent content by Avii13

  1. A

    How to provide clock skew in VHDL ??

    Can't it be done using same clock ??
  2. A

    How to provide clock skew in VHDL ??

    I have written a VHDL code for PRBS. Its working fine. Now i want to add clock skew to know the threshold value of delay after which PRBS will not work. Say clock reach at FF1 at T time and the same clock reach at FF2 at T+t1 time. I used process begin WAIT FOR 20ps ; if clk'event and clk = '1'...
  3. A

    2.5 Gbps PRBS Generator Schematics?

    Yes, I'm using discrete IC's and the same series. In my project I have to provide clock to two 2^7-1 PRBS with single clock source. As a clock driver I'm using insemi's NB100LVEP221. the output of two PRBS are fed to MUX to get a 1.25 Gbps output rate. For clock I"m using onsemi's NBXSBA024...
  4. A

    2.5 Gbps PRBS Generator Schematics?

    Re: prbs generator Hi, I am facing the same problem and have to design a PCB for PRBS Generator. If you have solved your problem please help me. Any schematic or tips ?? Regards Avii13
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