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Dear circuitking,
the range of the MOS operating region can be determined by gm over Id ratio (gm/ID=2/(VGS-VT)). Hence, if gm is in the range 5-10 S/A the MOS operates in strong inversion, the range 10-15 S/A is the moderate inversion and 15-25 S/A is the weak inversion. The MOS exhibits the...
Dear circuitking,
with discrete component I indicated the off-chip components (the SMD components). In your case I suggest to design an inductor. Even with 50 GHz the wavelength is too big for IC design. Moreover, to enhance the gain and noise performance try with a cascode configuration for...
Yes theoretically you can substitute the inductor with the transmission line but, as explained in post #4, in IC design the trace lengths are too small to implement the transmission lines at low frequencies. In my experience I've used the IHP process with a channel length of 130 nm that allows...
Dear circuitking,
your procedure is correct, but the synchronism condition must be take in account. To guarantee the same time constant on the drain and the gate lines LgCg = LdCd. In traditional MOS Cg > Cd, so a further capacitance is added on the drain line.
N.B. the gate capacitance Cg must...
Dear circuitking,
the design of a distriubted amplifier is quite different from the traditional CS amplifier. It comprises several mosfests (3-5) connected with two transmission lines: one for the gate and one for the drain. In IC design these lines are realized with a cascade of LC cell. For...
Dear Ironlord,
I'm not known the verilog language but you have to pay attention on these two code lines:
cur_inputs<=switches;
last_inputs<=cur_inputs;
in VHDL you are defined cur_inputs and last_inputs as two signals. So the value of cur_inputs will be update only on the next rising edge of...
Dear Friend,
the dimensions of a quarter wave transformer depend on two main paramenters: the impedence to match and the dielectric characteristics. Supposing to match an impedence Zin and the load RL, the impedence of the quarter wave transformer is Z1^2 = RL * Zin. For example if RL = 50ohm...
Dear Junus,
the saturation region depends on the gm over ID ratio that is equal to 2/(VGS-VTH). The weak inversion occours for gm/Id in range 15 - 25 S/A. Probably in your case with 60 mW you don't satisfy this criteria.
BR
Dear Sir,
I'm designing my first analog layout. In particular I'm designinng a conventional four stages Distributed Amplifier with SG13S process. When I introduce the inductors in the layout, I obtain a loss of gain of 2 dB due to the interconnection routes. Could you suggest me how can I...
Hi Avinash, the RF layout are very complicated. There are a series of techniques for minimizing the parasitics of the circuit. However the book "the art of analog layout" of alan hasting is a good starting point. Furthermore searching in google can you find Tutorial on simple lna design (for...
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