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Recent content by au_sun

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    Edit placement in MAGMA after fix cell

    Hi, I want to edit placement in MAGMA after fix cell. But when i tried to move manually, I am getting the error message stating that "the model is a readonly model" How to Edit placement manually in Magma after fix cell. thanx
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    Why we need to have setup/hold time for a flop?

    Re: setup/hold time setup time and hold times are basically is a requirement due to transistor characteristic.
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    Magma Blast Fusion Question - P & R

    cross talk is an issue which is know only after Final routing, Fix cell may size cell such in such a way that it can reduce some cross talk effects in the later stage. Magma can fix cross talk issues after routing. refer to documents fro cross talk solutions offered by magma
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    How is VLSI jobs in INDIA!!!! Has LAY-OFF started!!!!!!!!

    sasken layoff Hi Guys, How is VLSI jobs in INDIA!!!! Has LAY-OFF started!!!!!!!! i hearing that companies like Wipro, Sasken, Tata-elxsi are sending out their peoples silently!!! Is this news true or "a Rumor" Guys kindly share ur view on this!!!!!!!
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    MAGMA: Restricting Routing layers in Block level designs

    force model routing layer $m highest M6 -net_type signal will do the layer restriction
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    What kind of analysis can be done with SPEF?

    analysis with SPEF u can use it for Timing anaylsis & cross talk anlysis
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    Why we fix Hold after CTS?

    Hold after CTS the actual clock network delay will be know and the violation reported will be more realistic, So hold violation is fixed after CTS.
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    about calibre erc error

    erc calibre all erc errors should me removed !
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    what's the "logical tie-off cells" in soc encounte

    tie off cell Tie-off cells provide ESD protected logic levels '1' and '0' to be used for connecting transistor gates. the transistor gates in a design may be required to connect logic '1' and logic '0' permanently, ie VDD and VSS logic levels, It is usually tapped from near by Power lines...
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    how to fix problems when fails to post simulation

    Check your Design timing, first check whether ur netlist passes Timing Analysis check in the Synthesis tool. Ur design functionality may fail due to timing violation in ur design after synthesis......... check for it.
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    TIMING ANALYSIS( SOC ENCOUNTER)

    Until CTS done is done, u dont have proper information about clock tree. so u can judge better about Hold violation with Clock network delay information after CTS. But in the case of Setup, u will have delay information for the data paths, so u can check for setup violation in the Pre-CTS stage.
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    flat and heirarchial design in physical design

    In hierarichical design, Each blocks are implemented as a seperate HArd Macro and then they are integrated at the Top level. In Flat design, all the blocks are implemented in single flat netlist, there will no Hard macro implementation.
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    How to fix setup and hold violations?

    Violation question!! For fixing Hold violation between two registers, various techniques are there, 1. try to add delays cells in between the registers without violation setup timing 2. try to utlize usefull skew in the clock paths betwwen two registers. etc.. for Fixing setup, 1. try to...
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    Question about timing analysis in SoC Encounter

    Timing Analysis Definetly there will change in timing report,
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    65nm technology challenges

    Challenges in 65 nm, - leakage power, SI issues are more prominent in 65nm. SI can cause timing violations. Fixing SI triggered violation requires proper analysis. for Leakage power reduction various techniques such as using multi Vth cells, Power down circuits, are adapted during the design...
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