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I am unbale to create symbol in veriloga after clicking on save button as the tool doesnt even ask.
Also when I look into the parser file there are no errors but when I try to close the file it throws syntax errors but not the line numbers.
The code I am trying to run has not errors as it is...
Re: N bit Adc vams model
analog
begin
V(VREF)<+ 0.7 + (TRIM * 0.0266667);
max_1=V(VREF) + 0.6;
min_1=V(VREF) - 0.6;
// min_1=0;
fullscale_1=max_1+min_1;
midpoint1=fullscale_1/2.0;
end
always@( posedge (CLK_IN) or !(fault_avdd) )
begin
//if (!(fault_avdd))
// begin
sample1=V(VIN)...
N bit Adc vams model
I am modelling a 12 bit ADC in vams.
The input range is 0.3 to 1.5V. i.e 0.3 = 000'H and 1.2V = FFF'H.
Need your help in selecting midpoint values
max= 1.5;
min=0.3
fullscale = max-min;
midpoint = fullscale/2.0;
This logic doesnt work.
I have 5 to 6 if loops comparing different values like 0.6V,0.5V,0.4V. So cannot go with the above solution. I also tried with V(THRESHOLD1,GND)>0.699999 && V(THRESHOLD1,GND)<0.7000001 and its working..
Even in case statement I am not able to verify with 0.7 whereas other values are working
Hi All,
I am unable to enter this if loop,
if (V(THRESHOLD1,GND)==0.7)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(VDD);dummy6=V(VDD); end...
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