Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by aswin123

  1. A

    Help me build verification environment for sdram controller

    Re: sdram controller hi, thanks for u r reply regarding sdram controller. i have some more doubts? can u explain in systemverilog verification point of u/ what is the interface in sdram/ and how to interact with environment.
  2. A

    Help me build verification environment for sdram controller

    hi, i am working on verification of sdram controller. i don't have good material. can anybody send specification documents or verification code if available. and also suggest me how to build verification environment. thanks.
  3. A

    Synchronous and Asynchronous Design

    i agree with asynchronous designs consume less power. due to this in every design we can use asynchronous design only or synchronous also some times. what r the advantages in syncronous compared to asyncronous ........
  4. A

    What are the steps in backend design?

    Re: reg backend LVS - Layout versus schematic. after completion of layout we can compare layout with schematic diagram. if it is not match we can add some RC Delays(resistence and capacitence) in layout and equate both. at last we can get functionality same in both.
  5. A

    Que.Regarding Delay Back Annotation

    What is meant by Delay Back Annotation...........which delay is called this....how many times we can do this process..
  6. A

    How to use $setup,$hold and $width system tasks in verilog??

    verilog $width How to use $setup,$hold and $width system tasks in verilog. in which block we can use these statements (i mean always block or specify block) can anybody expalin me with example
  7. A

    Question Regarding VCS Tool??

    top 10 vcs tools if u dont mine can u expalin this sentence again......i am unable to understand parsing and vlogan p.s----i forgot to write one thing........the first step is the parsing of design files using vhdlan or vlogan ........
  8. A

    Good Verilog file io material..........

    verilog file io it's really useful
  9. A

    good timing material........

    timing material useful material in STA
  10. A

    Advantages of SV compared to verilog as a verification point

    Re: Advantages of SV compared to verilog as a verification p in System verilog verification & design same constructs can be used or different?all are synthesizable code or not???
  11. A

    Post Synthesis - Simulation

    can you suggest sysyem verilog verification books.......
  12. A

    Interface Block in System Verilog.................

    What is the Importance of Interface Block In System Verilog........Without this we able to Build Environment or not...... what we can put into the interface block and how it will help to remaining blocks in the environment..... Suggest me.
  13. A

    How to move into FrontEnd design process from BackEnd?

    Re: Moving into Front End Hello, Compared to backend ,Front End is easy in every aspect.i mean Getting job, Interview calls,materials,guidence etc... In BackEnd even u unable to get interview calls.if u wait 1 or 2 months u will get atleast 1 interview call as a fresher. but in digital ,not...
  14. A

    Question Regarding VCS Tool??

    vcs vcd to waveform Thanks for u r reply. VCD means value change dump,VPD means what???? and VPD file is generated after simulation.do u know what this file contains??? and it in ASCII format or BINARY format.
  15. A

    Verilog Code for Ethernet controller

    ethernet verilog Where to findout X-HDL tool , is it available in google or we want to go any other site. suggest me.
See more

Part and Inventory Search

Back
Top