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Recent content by aspirinnnnn

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    How to estimate the SRAM area?

    Very useful information!thanks a lot
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    SDF file generated by Prime Time cannot be back annotated correctly

    Help me a lot, problem solved, thanks very much - - - Updated - - - yeah , I did ,i solved the problem follow @sam536's method,but thanks anyway
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    SDF file generated by Prime Time cannot be back annotated correctly

    When I do the after P&R simulation in VCS , I encountered such a problem : the SDF file generated by the PT seems cannot be back annotated correctly, the SDF file can not properly back annotated with the .v file, the simulation result is wrong ( I observed the wave file ,there is...
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    How to estimate the SRAM area?

    thanks very much, I still want to know how to estimate the area by hand, may be the estimation is roughly right or relatively right will be ok - - - Updated - - - thanks very much, I still want to know how to estimate the area by hand, may be the estimation is roughly right or relatively right...
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    How to estimate the SRAM area?

    hi,everyone,I want to know how to estimate sram area in ASIC for example, I want to implement a two port (one for read ,one for write ) sram in ASIC , and the depth is D, words width is W , in a certain technology, how to estimate the area ?
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    Systemverilog interface Question

    I found that VCS don't support for this feature, is there any way i can work around this ? - - - Updated - - - I found that the VCS is not support this feature, is there any way i can work out this?? thanks a lot
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    about generate block in the SystemVerilog

    I have a generate block in SV like the following: genvar i; genvar j; generate for (i=0;i<8;i++) for(j=0;j<8;j++) begin:peBlockGen peLogic U_peLogic( .clock(clock), .reset_n(reset_n), .inst(inst), .din_self(din_self[i*8+j]), .din_up ( i==0 ? din_up[i] ...
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    Systemverilog interface Question

    thanks very much, and I figured why i was wrong ,if I using the slave_wren[0] or slave_wren[1] in the modport, it is impossible to reference it in another module with the same interface, I can't refer a signal as slave_wren[0]. and actually I want to ask you one more question Sir, since I have...
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    Systemverilog interface Question

    I have a interface like interface mAHB_bus #( parameter SLAVE_NUM=8 ); logic [SLAVE_NUM-1:0] slave_wren; logic [1:0] slave_size; logic [15:0] slave_wraddr; logic [31:0] slave_wrdata; logic [SLAVE_NUM-1:0] slave_rden; logic [15:0] slave_rdaddr; modport bus( output...
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    famous Electronic Enginering community or forum

    Sorry for the late reply. I visited The Designer's Guide Community Forum you mentioned, I find it is mainly focus on analog designs, I am more like a digital designer , but thank you anyway!
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    SystemVerolog Problem with VCS

    I am learning systemverilog ,so I started with a simple one. BTW, I found where i was wrong. the Instantiation of the interface should wrote like : half_adder_if ha_if(); but not ]half_adder_if ha_if
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    SystemVerolog Problem with VCS

    I had this code downloaded from internet ,and I want to run it with VCS ,but encounter such error: Error-[INIPL] Identifier not in port list Identifier 'ha_if' does not appear in port list. "half_adder_if.sv", 23 Source info: half_adder_if ha_if; the original code is shown below...
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    famous Electronic Enginering community or forum

    I am currently very intersting in integrated circuit design , computer architecture , are there any reputable online community or forms that I can blog share idea with others ?
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    Verilog Testbench to monitor signal relationship

    Thank You Very Much ,It Helps me a lot
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    Verilog Testbench to monitor signal relationship

    I am currently working on a CMOS Image Sensor controller. this controller has to give a huge control signals to the ADC and Pixel array. those signals has its fixed relationship like: a is pull up high for 10 clock,then pull down for 15 clock and ..... b is pull up high one clock...
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