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Recent content by ASICTiger

  1. A

    Map my module to a specific standard cell

    Thanks NotSam! I will use the standard cell name as the module name and see what I am going to have. Thanks
  2. A

    Map my module to a specific standard cell

    Hi Not Sam :) This is exactly what I want to do, structural for some part and RTL for the rest of the design. Now, could you teach me how exactly I can instantiate a standard cell in my HDL code? Let's assume that I have a cell called "XYZ", with "A&B" inputs and "C" output. How I can...
  3. A

    Map my module to a specific standard cell

    Thank you guys! All solutions looks valid for me. However, I wonder if I can find more straightforward solution. Can I name the module exactly as the standard cell name? Do you think this will make the synthesis tool use this standard cell for mapping? I am really shocked when I figured out that...
  4. A

    Map my module to a specific standard cell

    Hi Kahsh, Thanks for your reply, yah I understand synthesis very well. May be I did not make my point clear. I want to force the synthesis tool to use specific standard cell to map one of my modules. Think about it as calling one standard cell early in the front end coding. Thanks
  5. A

    Map my module to a specific standard cell

    Hello all, I want to map one of my modules to a specific standard cell. Any suggestions please ? Thanks Tiger
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