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Recent content by asicguygmail

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    Altera router estimated peak interconnect usage is above 100% in some areas

    Hi, I am having trouble synthesizing RTL using quartus. I get the error at the end of my message and routing fails which seems to be because of this. The interconnect usage is above 100% in some areas. I switched from Stratix 4 to 5 and also a to a bigger device and still see the problem. Some...
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    Problem using 8 USB to RS232 adapters with PC and windows XP

    Hi, I have to control 8 different devices from windows XP through RS232 interface. I purchased 8 USB to RS232 adapter and connected to my system. Hyper terminal works fine reading all adapters. The problem starts when I start reading/writing RS232 with C (or Matlab). I use Microsoft visual C++...
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    Why do I get this warning? " .... does not appear in the sensitivity list....."

    Re: Why do I get this warning? " .... does not appear in the sensitivity list..... I did try this and I get the same warning. I have also changed in_from_vn[1973][3:0] to in_from_vn[1973] and I get the same warning Thanks Alex
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    Why do I get this warning? " .... does not appear in the sensitivity list....."

    Why do I get this warning? " .... does not appear in the sensitivity list....." I get following warning because of the RTL that is followed. You can see that the signal in_from_vn[1972] (The same problem is with in_from_vn[1973]) that's being read in the always block IS in the sensitivity...
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    Why net (wire) delays are zero after synthesize?

    Thanks for the info. I have a huge design in which, we can not ignore net delays since the module is big and I use the biggest wire load model. Should I still get zero wire delays? Is there anything I can do to more realistic delays? The main problem in this design is wire delays and I want to...
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    Why net (wire) delays are zero after synthesize?

    Hi, I synthesize an RTL code with Synopsis. I add a wire_load_model to my synthesize process. At the end I do a report_timing and I see all gate delays but I don't see any net (wire) delays in the timing paths. This is the command that I use to add wireloadmodel: set current_design cnode...
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