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I'm trying to map a design generated low frequency clock of khz range to clock port of ILA core in chipscope PRo (.cdc) file. When I program and run the bitstream in fpga, it flags the message "Waiting for Core to be armed, slow or stopped clock".
When I tie the clock port to on board system...
chipscope PRO analyzer: Waiting for Core to be armed, slow or stopped clock
Hi
I'm trying to observe signals on waveform window in chipscope pro analyzer for viretex 7 FPGA on VC707 board. I get the message that "Waiting for Core to be armed, slow or stopped clock".
FYI, I've hooked up the...
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