Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by asic_guru

  1. A

    Verdi error: include file "define1.vh" cannot be read "/y/yy/define2.vh", 1:"

    Re: verdi problem 1. Check if the files exist at the given paths. 2. Has the file-list included those files, or the parent directory as an "incdir" ?
  2. A

    How to model dual stage synchronizer?

    What is the difficulty in modeling it into a single cell ? Can you please clarify, as I do not understand the problem?
  3. A

    Need tutorials for digital systems , netllist models etc

    You can use the foll book - https://www.pearsonhighered.com/educator/product/Advanced-Digital-Design-with-the-Verilog-HDL/9780130891617.page
  4. A

    new processor architecture

    The problem right now is that software is not able to keep up with hardware developments. We have parallel processors, but the parallel programming paradigms are not developed enough to harness all the raw power the processors provide. That is one of the reasons Intel's Larabee, the GPU , is...
  5. A

    problem in rtl simulation

    If I understand right, when you tested out the individual blocks, they produced the desired results. However on connecting them all together you do not see the desired overall output, is that right? The whole is always greater than the sum of its parts ! Did you check the connections ? Can you...
See more

Part and Inventory Search

Back
Top