Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ashish_soni

  1. A

    how to do constant current biasing in analog circuits

    Hi, I have a doubt regarding constant current biasing in the analog circuits. if I bias a circuit using the current mirror, it's current is going to be fixed. now if I want to change the gain, I have two choices a) change the gm b) increase the ro say I want to increase the gm, I can play...
  2. A

    [SOLVED] SAR ADC SNDR and other spectral analysis in cadence virtuoso

    Please find my DUT attached. Here capacitor bank forms DAC which has analog input as VIN+ and VIN- and Vref+ and Vref- are reference signals. SAR block is controlling the comparison. The output of DAC is going to the comparator where I'll get the digital output based on DAC output. I have...
  3. A

    [SOLVED] SAR ADC SNDR and other spectral analysis in cadence virtuoso

    What I could understand is to apply the input to DAC and plot the output of DAC just after the sampling instant. The applied input and sampled input on the capacitor should be same but due to quantization error, it will add noise hence I need to calculate the SNR at DAC output for my ADC. The...
  4. A

    DNL and INL analysis of SAR ADC

    Hi All, I am working on 14bit SAR ADC with a sampling frequency of 5KS/s. I am supposed to do DNL and INL analysis to get information about missing codes. what I know to do DNL and INL analysis is, apply a super slow ramp so that each code appears at least 10 times. Now my problem is, I have...
  5. A

    [SOLVED] SAR ADC SNDR and other spectral analysis in cadence virtuoso

    Hi All, I am working on 14 bit SAR ADC for biomedical applications with a sampling speed of 5KS/s. The DAC architecture is differential and dynamic range is 1vP-P. My circuit level part is completed and now I am heading towards SNR, SNDR, and other spectral analysis for getting ENOB. What I...
See more

Part and Inventory Search

Back
Top