Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello,
I am using genus tool for synthesis. I have the 2 different clock domains in my design but connecting the whole design into single scan chain.
I see tool insert a lockup latch when it is stitching the scan chain from one domain to another domain.
The tool inserted negative level lockup...
You need to declare output as state TYPE. And then simply assign the current_state to output. You don't need the output_gen process.
You can create a pkg, where you can define the state TYPE. And then import this pkg to declare output and current_state, next_state of state type.
One example of casez is to code a priority encoder (or servicing multiple interrupts based on priority). It makes easier to write the code, instead of writing multiple conditions using case statement.
casez ( intr [31:0])
32'b1zzzzzzz_zzzzzzzz_zzzzzzzz_zzzzzzzz : --------...
The multicycle path constraint is used between synchronous clocks (same clock or divided clock).
If clocks are asynchronous then no need to define the multicycle path. But you can still define the max delay for that path.
Here, the setup violation means that tool is not able to meet the timing...
If it case 2 (clocks are synchronous) then this should be okay.
For multibit data, you should always capture it only when you detect the rising edge of _vld signal.
so actually _vld signal works as a qualifier for data.
The time you detect the rising edge of _vld signal, data is already stable.
Case 1 : Clocks 125 MHz and 750 MHz are from different sources (async clocks).
From module 1 to module 2, you just need a synchronizer (may be 2/3 flops) for module1_valid signal.
From module 2 to module 3, again you need a synchonizer for module2_vld. The module2_vld should be @750...
2) clock to output delay
e to o1 : 0.2 + 0.4 = 0.6 ns
e to o2 : 0.2 + 0.4 + 0.4 = 1 ns
3) external setup time <= min clock period - max clock to output delay
<= 1.8 - 1
<= 0.8 ns
4)...
1) The max. freq. would be 1/1.8ns = 555.55MHz
5) To make the circuit work at 2.5 GHz (0.4 ns)
5.1) Delay the clocks for output flops, so that skew will be more.
-- for first output flop add 3 more buffers (0.6 ns)
-- for 2nd output flop add 5 more buffers ( 1 ns)
--...
According to spec..
• a write response must always follow the last write transfer in the write transaction of which it is a part
I am confused about the "follow" word. Does it mean that BRESP can'be combo output in the same cycle of input WLAST?
I was thinking a case where slave can still...
Hi,
Is it possible to complete one AXI 3 write transaction in just one clock cycle?
Provided This transaction has only one beat to write. And AWREADY, WREADY and BREADY are by default HIGH.
Lets say master sends the address and data in the same cycle (AWVALID, WVALID and WLAST in same cycle)...
Hi ads-ee,
Thanks for the detailed analysis.
In my design some flops need only RESET1, some need only RESET2 and some need both. So anyway I have to synchronize both the resets separately.
Now If I combine both of the resets and then put one more synchronizer, this will add 2 cycle...
Hi,
I am having two async reset inputs to my design. If I have to OR both the resets, where should I use the OR gate?
1. Should I synchronize(async assertion and sync deassertion) resets separately and then put an OR gate?
2. Should I first combine (OR gate) both the reset and then use the...
I do know that "default case" will not harm. But wanted to know that if we don't put any default case then what is intended from "unique case" and "enum types"? Do they make any difference to the tool?
It is obvious that different tool may behave differently but there must be some intention to...
Hi FvM,
I am mostly interested to know, will tool create latches for the code I mentioned?
I am using 2 bit logic to define 3 states using "enum". And using "unique case" statement without "default".
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
