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Recent content by ashiram

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    howto determine the FIFO Depth

    Re: FIFO Depth Here is the answer. input 500Mhz 16 bit Output 50 Mhz 1 bit Let us consider 500/50 = 10 . That means 10 clocks of input write, we can only have one clock of output read. in 10 clocks, How many data it can able to write = 10*16 = 160 bits. In read side, we have only one clock...
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    FIFO Depth tricky question

    fifo depth rules Here i am assuming write is happening continously. Read should happen continously but after 16 clocks. In that case take FIFO DEPTH of 15. Usually FIFO Full happen after 15 clocks. Check this condition and read the data out. As soon as Write data is written, read data is read...
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    NVIDIA Interview question? ASIC Verification

    nvidia interview process I can go for functional coverage and code reviews. This will solve some bugs in Testbench.
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    NVIDIA Interview question? ASIC Verification

    nvidia interview Yes , The mistake is in BFM and Design too.
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    Simulation vs Verification ?

    Simulation means debugging functional errors in in the DUT. Verification means Creating test bench and writing test cases . checking DUT functionality after running testcases.
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    Looking for some good OVM tutorials

    ovm tutorials Hello, Please check below URL. https://www.doulos.com/knowhow/sysverilog/ovm/ You can easily understand basic concepts of OVM Thanks, Ram
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    NVIDIA Interview question? ASIC Verification

    verification interview questions But protocol checker will be developed by Verification engineer. If that is wrong, errors will occur.
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    which verification methodology to be used??

    Now a daya, Systemverilog has become very popular for functional verification. Most of the companies changing their Verilog test bench to system verilog test bench. Lot many OOPS concepts are introduced in systemverilog to achieve reuseability of data objects Thanks, RAM
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    NVIDIA Interview question? ASIC Verification

    asic verification interview questions Hi every one, Yesterday i got an interview with NVIDIA. They asked one intresting interview question. What if design engineer and verification engineer do the same mistake in Test bench BFM and RTL(DUT)? How can you able to detect errors...
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    VMM Notify functionality with respect to VMM transactor?

    Hi everyone, Can anyone please explain what is the purpose of VMM notify? I understood,it is like event with status mesage. Instead, i can use display(),`vmm_note. But what is the additional advantage we can achieve by using this? Thanks, Ram
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    VMM Notify functionality with respect to VMM transactor?

    vmm notify Hi everyone, Can anyone please explain what is the purpose of VMM notify? I understood,it is like event with status mesage. Instead, i can use display(),`vmm_note. But what is the additional advantage we can achieve by using this? Thanks, Ram
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    What is a "callback" in Systemverilog?

    callback in system verilog As per Systemverilog Perspective, Callbacks generally used to store expected data and check DUT Data against expected data. These call backs are called before transmitting and after receiving data. Added after 54 seconds: As per Systemverilog Perspective...
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