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Recent content by ashgun

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    System verilog :: Why need Casting between parent and child

    Re: SystemVerilog :: Why need Casting between parent and child Thanks dave for the Reply I have a question about this from the above code a = b; b = null; Why will ever we have to store the handle of object of class B (Derived class) in object of class A (Base class) . Is there any...
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    System verilog :: Why need Casting between parent and child

    HI Team , I have a quiery about why do we actually need Casting between Parent and Child Class . Actually the confusion is why do we need to have Parent class being assigned a child class's Handle . Once we Pass the handle we do the casting . My question is that If we know we need Child...
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    perl : ssh/rsh on a machine

    perl ssh password Hi , I need help on this issue . The thing is I am trying to do RSH/SSH on a machine from perl script , When its asks for password --> I enter the password but then the further lines of the script does not execute untill I logout fromm the Remote machine . How Can I...
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    Help me use awk command in Perl script

    using awk in perl Hi all , I have been trying to use awk in the perl script but some how I am not able to extract what i want it to . I want to read a file and print $9 into my array but somehow Iam getting the complete line in the array . Here is the code @one = ` awk...
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    pre and postsynthesis simulation mismatch please help

    This problem can come If all of your Registers or the signals in the always blocks are not initialised properly . If you have not initialised any of the Signals used in the always block you will get X and it will propagate throughout your Design . Try checking that . Also try checking IF...
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    Glitch detection in RTL using Spyglass/Conformal/Debussy

    Re: glitch detection HI You can not have this type of design in actual Design . In clock Domain passing the signal passing from one clock domain to other cannot pass through Combinational logic . It has to a registered signal .
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    Specman Experience 1 year .. Need job

    Hi I have worked on specman for one year , looking fo a change . People who are working in Companies working on Specman in INDIA can send me a message at luvash625@hotmail.com . Its urgent Thanks in Advance
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    Synthesis of STATE machine Verilog

    Hi all i want to know about the sythesis of state machine in verilog . basically we say that CASE statement synthesizes multiplexer and we use CASE statement in STATE MACHINES also so can any body tell me the what it will look like in Hardware means using muxes gates or some higher level blocks...
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    default value of wire in verilog = 0

    default value of wire in verilog Hi all i need some information for making the default value of "wire" in verilog to 1 or 0 as required and after that whenever needed change its value . is there any way to do that .
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    What are the tools for Vera and Specman?

    Re: Vera and Specman Specman is a tool which works on code written in E .
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    How to generate 125MHz to synchronize RXD for MAC CORE?

    Re: MAC IP CORE design When you are using TBI mode in 1gbps mode , the phy provides 2 clocks of 62.5 Mhz , but as you are working in 125 Mhz clock on your mac side you will have to use that clock to synchronise the data for MAC Core
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    Ethernet MAC MDC frequency

    MDC is a clock for management interface and it has to be 2.5 Mhz ..
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    ETHERNET TBI mode ... Quiery

    tbi mode HI , i am little confused about the EVEN position Funda in Tbi , as i am testing Tbi mode in ethernet And there are test case which take thsi EVEN position Funda , that COMMA patterns shouls be in even position .. but how do i ascertain the even position i know little...
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    UNIX command from NCSIM prompt

    Ho wcan i run a unix command from the ncsim prompt . Thanks Ash
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    Question about Vlan tag in the ethernet

    Vlan Tag Hi i have a doubt about Vlan tag in the ethernet .. they are Vlan tag has 4 bytes 1) first 2 bytes remain same 2) what is the meaning of the other two bytes .. actually it is explained in IEEE P802.1Q® but i dont have it i tried searching it on google but nothing came up...
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