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If the LPF is made from passive elements I prefer to have a buffer as 1st stage, RFI, another buffer, and LPF. So the overall performance is not a function from the signal source impedance. This scenario assumes IA as a buffer.
Please check that you are showing a right schematic. Pay attention: The gate of pmos transistor is connected to drain of nmos(excellent pull-down condition), but when Vgate of nmos less than threshold voltage the second pmos transistor is in unknown condition.
Try do the same measurement with 1/4, 2/4, 3/4, 5/4, 6/4,7/4 off 125MHz clock frequency; and check if the data acquisition clock and adc sampling clock have been changed proportionally. Good luck!
Couple suggestions:
1. Check Environment (Setup/Environment/Switch View List). Must contain "veriloga"
2. Use resistor models from built in libraries: ahdlLib (veriloga model); and analogLib (spice model). See if you are able to probe currents/voltages/dc operating points.
If the result is...
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