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Best answer.
One more thing to add: The cell that sinks the most causing large IR drop is usually having a large load cap. Consider lowering load along with the drive strength.
Let's get into context. For memory, we have a few solutions at hand to fulfill our need: SRAM cells, latches, or registers.
Basically, latches and registers are made up of multiple digital logics. Because they are CMOS structure, their gate output Vout is independent of input Vgs, The output...
When a power domain of logics are turned, all its outputs become "unknown". For an inverter, it can switch to LOW when there is a HIGH input. But the reverse cannot be said when its input is driven with a LOW (it will enter into metastable state). This is why outputs of power-gated domains...
At the top level the worst path will be any path in the top level. At "current_instance <hier>", the worst path will be only the worst path within that particular <hier>. Check that you have the exact same timing path reported in both cases.
Hi kls,
Current design basically "switches" to another design, and does not go deeper into the hierarchy. What you should be using instead is "current_instance top/hier_you_are_interested/module"
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