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Recent content by arve9066

  1. A

    Switching supply sees short circuit for very low load resistances

    I just now tested the new unit after I ran out of all troubleshooting options with the new one.. Since the other one worked partially I did not realize it was defective for a long time. The mode of failure is what made me go in rounds a bit..
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    Switching supply sees short circuit for very low load resistances

    I did test another one of these packages and that one worked just fine. I was curious as to why the other one would not work below a certain load resistance alone. I tried different loads and anything below 75ohms, I get flat 0V at the output.
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    Switching supply sees short circuit for very low load resistances

    I am using the Murata OKL-T/1-W12 to produce 1.7V from a 12V battery. This 1.7V has to power a thermoelectric cooler of resistance around 2.5 ohms about 700mA load current. Although I see an open circuit voltage ( even with 1Kohm load as well) of 1.7V, when I connect the thermoelectric cooler I...
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    Formal port/generic is not declared error - VHDL

    I have uploaded the two files in which these parts of code show up. There are other project files as well which I am not including to
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    VHDL - generate signals from other signals

    I did get the thing working by getting the numbers right. I have no phase lag now between the two signals. But I will implement the same using counters as it seems the right way of doing it. Thank you very much for the suggestion.
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    Formal port/generic is not declared error - VHDL

    entity wb_sl_adc is generic ( NR_OF_DBGPORTS : positive := 1 ); Port ( syscon_i : in rec_syscon_port; master_i : in rec_master_port; adcclock_80Mhz : in STD_LOGIC; data1 : in std_logic_vector(13 downto 0); data2 : in std_logic_vector(13 downto 0); of1 : in...
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    VHDL - generate signals from other signals

    I did not fully understand the method you have specified. Could you explain a bit more so that I can understand it better. I am pretty new to this as you could guess.. Also I do understand that the if statement implementation is not the pretty way of doing it, but if I get the numbers in it...
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    VHDL - generate signals from other signals

    I need to have 8192 samples of ADC data between two samples of time which I do get with this code. So I do not think there is a counting problem in that part of code. I count from 0 to 8191 which gives me 8192 samples and at the 8193rd sample I make the time_ack=1 and set counter ADC_Timecnt=0...
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    VHDL - generate signals from other signals

    adc_clock80MHz is an 80MHz clock signal; First I count this clock and when it reaches 8192 I keep time_ack=1 for 1 clock cycle of the adc_clock80MHz. Now I count time_ack using timelog1 and timelog2. When timelog1 is below 64 I keep cal1 as 1 and if it is between 64 and 128 I make it 0 and above...
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    VHDL - generate signals from other signals

    process(rst, adcclock_80Mhz) begin if rst = '1' then ADC_Timelog <= (others => '0'); ADC_Timecnt <= 0; elsif adcclock_80Mhz'event and adcclock_80Mhz = '1' then ADC_Timecnt <= ADC_Timecnt + 1; time_ack <= '0'; if(ADC_Timecnt = 8192) then ADC_Timelog <=...
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    [SOLVED] VHDL Programming Help

    process(rst, adcclock_80Mhz) begin if rst = '1' then ADC_Timelog <= (others => '0'); ADC_Timecnt <= 0; elsif adcclock_80Mhz'event and adcclock_80Mhz = '1' then ADC_Timecnt <= ADC_Timecnt + 1; time_ack <= '0'; if(ADC_Timecnt = 8192) then ADC_Timelog <=...
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    MATLAB varying no of variable reading

    Ok.. Actually I am running another m file to create those mat files. Is there a different way I can save those variables to the mat files which will help me access these in the way I described earlier. My program does this - I have a varying number of input files which needs to be processed...
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    MATLAB varying no of variable reading

    I mean once I load the file in to matlab, how to access those variables in a loop if I know 'n'.
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    MATLAB varying no of variable reading

    I have a mat file that contains variables named deterministically like a1_1,a1_2,a1_3.... a1_n.. n is variable depending on the mat file I read, but the naming convention remains the same. I need to read all of these in a loop that goes from 1 to n. What is the best way to achieve this?
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    PSD vs FFT Magnitude squared

    Suppose my time-domain signal is a voltage signal. I sample this at the correct rate, and taking the Fourier transform gives me the magnitudes of of various frequency components present in the signal (within the context of sampling rate). Taking the modulus squared of this quantity will give me...
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