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Hi
Power supply design is a wide area. You should get educated on the topologies first. Then you bring up your design specifications. It is convenient to help you if you ask a specific question. Here are some links to get introduced to switching regulators.
**broken link removed**...
Hi,
Your above calculation will result in 11.08V which is wrong. The calculation goes like this https://obrazki.elektroda.pl/2800079700_1418056556.jpg. I hope attached solution explains everything.
regards
Arun
Hi,
You are missing the feedback loop which regulates the line/load in your breadboard implementation. You can google for the control techniques for the boost converter. There are voltage & current control techniques also, PWM & PFM techniques. However, if you don't need the regulation (meaning...
Hi,
w.r.t NMOS, the drain will always be at higher potential than the source & body. Recollect that in CMOS IC, NMOS body is always connected to least potential.
In the figure, you can witness the drain-body diode is readily reverse biased.
Hence we are not bothered about the body effect...
Hi,
If you apply 24V at the gate, you are exceeding the maximum Vgs rating of +/- 10V (as given in the datasheet). This will cause the oxide of the MOSFET to damage & the MOSFET will fail.
I recommend using a DC to DC SSR (Solid State Relay). Again it uses a optocoupler for isolation & switching.
Hi,
The model file basically consists of the details regarding an component.
Ex: when an nmos is called, the SPICE will look for the nmos model in the model file. It contains the details like Ids formulae for all the 3 regions (cutoff, linear & saturation). The SPICE will put the user entered...
Hi,
Differentiation & Integration are the base of any electronic component. Consider RLC,
R has linear relationship of V= IR
L has a relationship of V = L(di/dt)
C has a relationship of I = C(dv/dt)
As you can see the di/dt & dv/dt in L & C respectively are the delta function. It defines...
Hi
My replies are in blue.
1. If we are not meeting spacing which is mentioned in DRC.
Initially, your layout design tool signals DRC error. However if you neglect the error, after fabrication, the metal lines could have shorted. This will fail your entire chip.
2.What is the difference...
Hi,
I have designed the circuit & layout of an synchronous buck converter in 180nm technology (in Cadence). Now I am trying to implement the I/O pads around my core design. I do not have prior experience. Hence, please guide me the basics & the important considerations.
my converter output is...
Hi,
I am designing a synchronous buck converter & the specs are as follows:
Vin = 1.8V
Vo = 0.5V
Io = 1mA
Fsw = 1Mhz
Vripple(p-p) = 500 micro volts
For this I need to design error amplifier. My understanding is that I need to design a two stage op-amp with input differential amplifier...
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