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Recent content by arun_prabu

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    I need help with Wireless USB

    cordless mouse or keyboard does not obey USB protocol. They make some changes in the protocol stack and transmit the data wirelessly. USB supports multi-level star topology.
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    What should we do if we get setup violation during tapeout?

    Re: set up violation The chip can work with a reduced frequency
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    corner cells ,scribe seal , filler cells

    filler cells and corner cells Corner cells - For pad ring connectivity. Had heard about die seal (it is between the border of the chip and the scribe line)... but not scribe seal.
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    Setup and Hold time violations

    Re: CROSSTALK If the aggressor and victim are moving in the same direction, the victim net switches faster. This may lead to hold violation. There will be a setup violation if both the aggressor and viction are switching in different direction. (In this case, there is a crosstalk induced delay...
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    Implementing a Latch using a Flip Flop ???

    Whether this will work? Data to D pin of the FF. Data -> buf -> Input A of XOR Data -> buf -> not -> not -> not -> not -> Input B of XOR Output of XOR -> Input A of AND Clk -> Input B of AND Output of AND -> CLK pin of FF regards, Arun
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    Reg: victim and aggressor net

    reg aggressor Nets switching at high frequency (Ex: clock nets, High freq data nets) (Aggressors) affect the nets adjacent to it (victim). This is due to the coupling capacitance between the two nets.
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    Which tools can do cell charactarization?

    NanoChar and Liberty NCX from Synopsys Silicon Smart Cell Rater from magma
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    negative propagation delay buffer

    It is true negative propagation delay can be achieved. I had heard about negative propagation delay inverters. Suppose if the consider any voltage below 20% of VDD as logic 0, and if the input changes from logic 0 to logic 1, in a negative prop delay inverter, the output goes to logic 0 before...
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    fixing setup violation using clock skew

    There may more than one path through the combinational logic between the two FFs. We consider the maximum delay path between the two FFs for setup and minimum delay path for hold violations. So, if we increase the positive skew, we can avoid the setup violation with respect to the maximum delay...
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    What impact does via have on yield?

    What impact does via have on yield?
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    Need Chm reader in linux

    download and install kchm
  12. A

    Looking for some materials to learn about VI Editor

    Re: VI superpower in EDA "Learning the vi Editor - O'Reilly publications" is a good book to learn abt vi editor
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    What does the __END__ in Perl signify?

    Re: Perl __END__ Go to www.esnips.com and search for it. u'll find it.
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    Article about using VI on UNIX systems

    Re: Using vi Sun keyboard + vim editor combination is really good.

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