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Recent content by arun397

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    warning in xilinx ise11.1

    Xst:1898 - Due to constant pushing, FF/Latch <Word_0> is unconnected in block <BW>. there are few more warnings like this. i dont understand what to do. please help.
  2. A

    warning during synthesis using ISE11.1

    please someone help iam running out of time. please, i am not able to understand what to do...........
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    warning during synthesis using ISE11.1

    i have attached the complete code as asked ............... please i would be very grateful if some one could answer it quickly please
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    warning during synthesis using ISE11.1

    hi i am getting the following warning during synthesis of my design. WARNING:Xst:1290 - Hierarchical block <BW> is unconnected in block <RxTop>. It will be removed from the design. and due to this the particular component is removed from the design. my component declaration and port mapping...
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    problem with chipscope

    hi, if any one could provide any specific example regarding this i would be very grateful. as i am not able to do it. thanks
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    problem with chipscope

    hi, thanks for the replies........ i have one more doubt. i have many components in my code. i am not able to understand what all nets to be connected to the trigger and data signals. i thought of connecting the top module nets but all the inputs and outputs are not available and many...
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    problem with chipscope

    hi, i have been using chipscope for my project. but it gives waiting for upload when ever i trigger.please help [/img]
  8. A

    about driver development for USB

    hi i have been posting quires about my project here. thanks for all the replies. my project is USB Device Core development on FPGA. i would like to know whether it is need to develop drivers (for the device developed) to be detected or can i use the windows drivers itself. and i have to use...
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    regarding USB device core development on FPGA

    sorry i did not use utmi.
  10. A

    regarding USB device core development on FPGA

    the code is in verilog
  11. A

    regarding picoblaze supported FPGAS

    hi, i need picoblaze processor in my project. but i have a spartan kit that has CPLD coolrunner. and similar kits like vertex4 etc. but all have microblaze. i would like to know whether is it possible to build this picoblaze processor on any kit or i need a specific FPGA which supports the...
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    regarding USB device core

    if no advantage what could be the possible applications by this
  13. A

    regarding USB device core

    hi, what is the advantage of developing a Usb device core on FPGA..... where can we use it............ thank you
  14. A

    regarding start of frame packet in USB

    so u say i need to include it in my code to receive SOF from the host......... i did not get u exactly can u be more clear please..........
  15. A

    regarding start of frame packet in USB

    hi, i have earlier posted few posts regarding my project USB device core on a FPGA ...... i would like to know whether a SOF packet is required to be added(written) in the code for a USB device ............... thank you.........
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