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This is what i've learned about jogs. From the above diagram, lets say we are working on a 90nm technology, and the minimum width of M1 metal layer is 0.12µm. Now the places where ever we see an edge having less than the minimum DRC (design Rule check) (ie less than 0.12µm) is considered a jog...
Looks like i've finally understood that OD2 would be an implant layer, which would change the doping concentration underneath a transistor (this is mainly done to vary the Vth (threshold voltage) value as per the circuit designers requirement. For example if the Vt value of a normal transistor...
in the above diagram (NMOS), the source and drain are highly doped (n+), where as the p-substrate (body) is lightly doped (p-), can anyone tell me why the body region (channel region) is lightly doped. Is it because we need to achieve a low threshold voltage?
I've heard from other sources that...
"In the next section NAND and NOR gates will be covered. (NAND are inverted AND gates) and (NORs inverted ORs gates). They both are single stage gates, and this is one reason why they are the basic blocks of CMOS logic."
Based on the above text, can anyone let me know what are single stage...
Re: may i please know what are "jogs" in digital or analog layouts.
This is what i've understood from the internet search and from what people have said.
From the above diagram, lets suppose that all three A, B, C are all M1 layers.
So what i've understood is that, A is...
Thick Oxide (OD2) Layout Rules
Define thick oxide area of 1.8v or 2.5v I/O transistors
The OD_25 Layer (CAD layer: 18) is used for 2.5V gate oxide area.
The OD_18 Layer (CAD layer: 16) is used for 1.8V gate oxide area.
OD2 refers to any thick oxide device, for exmple OD2=OD_18, OD_25.
Based...
For example in the above image, we can understand that, the Nwell will have a higher doping concentration at its edges. But when we consider the OD layer, the <AND> operation of the P-implant and the OD layer is what creates the diffusion (ie the sorce or drain). So like the N-well, the edge of...
in the 28nm design rule file we have a topic called "RV Layout Rules", and they have mentioned the below lines there
"Please allow sufficient RV counts to provide enough currect for EM and ESD protection. There it is recommened to put as many RV holes as possible.
My question is what are "RV...
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