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Recent content by arnoldwbush

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    [SOLVED] VHDL - Combinatorial feedback loops in JK FF but not in D FF

    Ah, thanks FvM After inserting a transport delay, the issue of uninitialized outputs is, indeed, resolved.
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    [SOLVED] VHDL - Combinatorial feedback loops in JK FF but not in D FF

    I will read up on the ring oscillator to better understand your comment. Do you recommend any specific source for that? Meanwhile, I wired up the master-slave JK FF as follows. My JKFF looks like: architecture Behavioral of jkff is signal a, b : std_logic; signal q_i, qb_i : std_logic := '0'...
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    [SOLVED] VHDL - Combinatorial feedback loops in JK FF but not in D FF

    Hi That's similar to my original code. Nonetheless, I pasted your code, fixed a minor typo and simulated it. The result is: Thanks Arnold
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    [SOLVED] VHDL - Combinatorial feedback loops in JK FF but not in D FF

    Hi FvM Thanks for the reply. First off, this is an academic exercise and I am trying to understand the objective behind this. I can simulate a JK FF using behavioural syntax (if-else) but not using logic gates. I was a bit inaccurate in my statement. I am simulating it. By "synthesize", I meant...
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    [SOLVED] VHDL - Combinatorial feedback loops in JK FF but not in D FF

    Hi everyone Consider the JK flip flop schematic below: I write the following VHDL code for it: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity jkff is Port ( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC; qb ...
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