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Recent content by Armoric

  1. A

    How to create a Bond pad?

    top and bottom layer is ok. but in the area of bond have to layout with top/bottom solder. the pad as usual without any defferent.
  2. A

    syntax error in header file

    i think that it would write the #ifndef ----#endif
  3. A

    How to compress a file to upload it here?

    Verilog Hi u can upload them to some web,and give our the link.
  4. A

    Where to get Modelsim ?

    modelsim the Mentor's license can be use in any soft that buy from Mentor
  5. A

    Which language is easier and better, Verilog or VHDL?

    Verilog Vs VHDL i think Verilog is easy to learn. and thd VHDL is goog for describe

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