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Recent content by Aritra Mukherjee

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    design of counters..pl help!

    First of all covert the input in parallel if its in series then using logic gates design a combination that gives one only when 5 is pressed and this output goes to an adder which u can monitor easily......
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    k-map

    bro do you know gray code??? Actually the binary numbers that we right is gray code..... Similarly the K-map works in a reflection like a mirror line. you pair all those where we can draw a symmetry in between..... below is a 5-6 bit Kmap...... but it explains theory for more number of...
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    Clock switching

    Hey Shanmugaveld thanks for posting it..... its very good.
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    java sites to learn about java

    I think bro we shud include some of the books of java and that wud help a lot to learn the language..... E-books are easily available on the net....
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    Verilog HDL - Book Recommendations

    **broken link removed** download the verilog material. If it doesn't works den reply me positively...... In that case i have to upload it somewhere n then send u d link......
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    can someone explain group carry look ahead adder

    Also this site has a good video of group carry adder. With the visuals its easy to learn and its better https://www.wisc-online.com/Objects/ViewObject.aspx?ID=IAU8307
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    Error Detection

    Please anyone please help me. I am stuck with the following codes n i don't know why it is not running..... `timescale 1ns / 1ps module SWT(input [1:0] a, output reg [1:0] b); integer i=0; wire [1:0] t; assign t <= a; always @(t) begin for (i = 0;i <= 10;i = i+1) begin #9000...
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    can someone explain group carry look ahead adder

    hi there sana..... u can try out this following link if still u don't get it den message me the xact part where u don't get it.... **broken link removed**
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    can you anybody give me the solution for this threat?

    hey bro cud u give me a small hint of what logic u trying to implement so i can help u on it otherwise its difficult to begin with..
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    code for 4:1 mux in verilog?tell the difference

    module MUX_4_1( input [3:0]i, input [1:0]s, output o ); assign o= (s[0]==0)?((s[1]==0)?i[0]:i[1]):((s[1]==0)?i[2]:i[3]); endmodule
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