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Recent content by Arik

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    Gate-count is NOT a library independent measure any more ?

    Re: Gate-count is NOT a library independent measure any more Thanks for reply iwpia50s However, are you sure that it is the only explanation of the phenomenon ?
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    Gate-count is NOT a library independent measure any more ?

    Hi all, Recently, I was working with 2 different cell libraries (90nm, 65nm) and noticed that there is a difference (up to 30%) between gate-count numbers of the same design for these 2 cell libraries. For both cell libraries I took the area of a 2 input NAND gate as a reference. The...
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    Parallel blocks in Verilog

    OK, avimit The parallel block in Verilog is really unsynthesizable and is used for simulation purposes only. Finally I have clarified this question for me. I did some experiments with ModelSim simulator, tried all 4 available combinations of 2 considered Verilog constructs: parallel/sequential...
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    What's the difference between always @ (posedge clk) and @ (posedge clk)?

    Re: Always Block the difference is that when you write @(posedge clk) it's just a conditional statement, which checks for clocks positive edge. And always @(posedge clk) is continous by its nature and is usually used for modelling of synchronous logic like flip-flops.
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    Parallel blocks in Verilog

    So, you mean that parallel block defined by the fork and join keywords is not synthesizable ? If it is not then it means that parallel block is intended for simulation only.
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    Parallel blocks in Verilog

    sequential and parallel blocks in verilog thx avimit for response By parallel block I mean the block specified by keywords fork join in Verilog. And by sequential block I mean the block specified by keywords begin end in Verilog. I think that any behaviour requiring parallelism could be...
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    Parallel blocks in Verilog

    sequential and parallel blocks verilog Hi What's the difference between parallel block and a sequential block with non-blocking assignments ? In other words is there any parallel functionality that could not be implemented with non-blocking assignments inside sequential block and requires a...
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    Can I use a SAIF file generated @ 27 Mhz

    In order the power reports to be accurate you need to make the SAIF files from netlist simulation. Though, sometimes, the netlist simulation of large designs can take a long time, so you can make the SAIF file from rtl simulation, but in both cases it's necessary to keep the original frequency...
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    Power Optimization of Digital CMOS VLSI Circuits

    Hi trungnl, The power optimization topic is quite large and it is hard to discuss it inside one post. Better you'd do some research on the internet and find papers/articles/books about the topic. Regards, Arik
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    Why Hold time is not considered while calculating max freq?

    setup time,hold time and max frequency Hi carrot, Actually the max frequency is limited by the total maximum delay of combination logic between two flops including flop's setup time. So setup time should be considered during max frequency calculation. On the contrary the hold time of a flop...
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    Power Optimization of Digital CMOS VLSI Circuits

    Hi vijai Actually the power optimization of CMOS VLSI circuits includes a lot of techniques that can be applied on different levels of abstraction throughout design flow. I think you need to start from studying the types of power dissipation in CMOS VLSI circuits. And then you can proceed with...
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    Help on ASIC Power consumption

    AFAIK there is no a direct way to measure the power consumed by ASIC. Instead you need some software tools like Synopsys Power Compiler/PrimePower.
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    How to get SAIF file ?

    modelsim saif AFAIK except VCS all other simulators that support the PLI interface need to be configured in terms of giving them an additional parameter which shows the path to PLI library file. For example for NCverilog on SUN platform you need to add the following command-line parameters when...
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    How to get SAIF file ?

    how to generate saif file You can also use simulators supporting Synopsys PLI interface for SAIF generation like NCverilog, VCS, ModelSim.
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    power report issue with Power Compiler ...

    thx moorhuhn for response !!! I have used the top-level .sdc to define the clock activities but I'm not sure if I have propogated it through the whole hierarchy. Tell me please what means to propogate .sdc through design hierarchy and how it should be done ?
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