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Hi ,
My memories/macros .lib has internal clock insertion delay defined on CLK pin of memory/macro with propert max/min_clock_tree_path . we have concern over register to memory paths where capture path is memory.
If i consider one register to memory path . Tool is balacing well register with...
hello all,
I am very new to use skill.
what is my goal is
i want to select all the pins from the current layout window,
i got the pin names using the geGetEditCellView command,taking in one varible and variable~>sigNames
now i want to select all this pins in the current layout window ,how...
helloo,
actually i need to decrease the run time of dynamic power analysis in voltus..... how should i proceed.. what will be the appropriate suggestion?
drc will be affected by using ndr rules? how to fix them up? can one relax ndr to res
drc will be affected by using ndr rules? how to fix them up? can one relax ndr to resolve drc?
thanx in advance.
common sharath666...... i know it is provided in db files with different combination of making d flipflop. it will be different for different d flipflop based on their internel design.... but how it is calculated????
well.... this was one of my interview question..
plz explain me the about the metal layers how they are arranged i.e vertical as well as horizontal layers with power rings,stripes and rails.
thank you in advance....
:smile::smile:
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