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Recent content by arc

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    sub ADC conncetion in pipelined ADC

    Friends, Herewith i have attched the circuit.... which is nothing but 2 dynamic comparator..both are identical. i want to build the first stage(sub ADC) of pipelined ADC.... can anyone tell me how do i make the connection??? how will i decide the vrefp and vrefn.... my FS voltage is 1v? Thanks
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    Question about the sub ADC stage in pipelined ADC

    Hello friends... i am designing a 1.5bit stage pipelined ADc. i have a question about the first stage that is sub ADC how do i decide the threshold and Vref for both the comparator.....so i will be able to get all the combination of output.... means 00,01,10,11.. etc... Thanks
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    Question on OPAMP simulation in Cadence

    My friend, i have asked for cadence simulation not the theory from book.... please let me know or upload if u have related information.,...
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    Question on OPAMP simulation in Cadence

    op amp simulation in cadence I am simulating Folded Cascode opamp What are the steps for DC analysis in Cadence? My main concern is which voltage source i have to sweep.... its a VDD = 1.8v ( by assuming using 0.18 tech)... or by sweeping Common mode Voltage source(VCM=VDD/2) connceted at the...
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    differential amplifier with CMFB

    from wher i will get "Cadence - Functional Verification of a Differential Amplifiers" this document... if any one have can please upload it. Thanks
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    Explanation of the latch comparator operation

    Re: latch comparator can you please elaborate more... my input signal range is 1.6V p-p...?????
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    How to develop the verification environment with Specman E

    Hi.... i want to learn the e language and how to develop the verification environment with it??? Also i would like to know more about specman elite..... can anyone give me some more information or passed it some material... Thanks
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    differential amplifier with CMFB

    Hello Friends.... i am looking for high gain amplifier.... the Diff Amp with CMFB is the good choice... can anyone give me some detail research paper or related book.... I required the designing and testing enviorment related stuff... if anyone of you have experience with cadence analog...
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    Explanation of the latch comparator operation

    Re: latch comparator can anyone explain me... how we will decide the value of +Vref and -Vred in pipelined ADC circuit.....please find attachment
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    Explanation of the latch comparator operation

    hi... can anyone give me the operation of latch comparator....??? also how to simulate the design in cadence analog environment.... Please help me out its urgent... Thanks
  11. A

    INTEL INTERVIEW- urgent need help

    hi all.... i have a interview with Intel, next week... the position is asic design- new grad.... can anybody share their experience of interview or the questions they wil ask??? Thanks in advance.
  12. A

    vhdl/verilog code for ieee 1394 project

    can any one help me to understand the ieee1394 architecure and desing using verilog or vhdl?????
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