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Recent content by aravind9

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    Low Power : Power Shutoff for Memories through UPF Power Intent

    How to shut off a memory(ASIC) which is in OFF power domain? (Constraints in design: Unable to power off a memory as it is always powered up and cannot add a power switch cell for a memory supply voltage) Is there a methodology to shut off a memory separately in UPF...
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    Concepts of Synchronization

    1. How to overcome the convergence and Divergence in the crossover path? 2. What is the difference between Dual Port RAM Synchronizer and Asynchronous FIFO Synchronizer? 3. Why the Dual Port RAM is having less area when compared with the FIFO memory?
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    Round Robin Arbiter using Verilog HDL

    Thanks for your response. I tried with what you have provided hint else if(req1 && !req2) ...... else if (req2 && !req1) ...... else if (req1 && req2) ...... For this I'm getting output like gnt1 = 1 , gnt2 = 'X' - - - Updated - - - The condition is like to avoid the contention when req1 and...
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    Round Robin Arbiter using Verilog HDL

    This is the Verilog HDL written for Round Robin Arbiter for two simple requests. When the req1 and req2 are high it should grant both requests in consecutive clock pulses, but this is not working when both requests are high. Please help me with this ASAP. module round_robin_arbiter( input...
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    Validity of the output signal in a Digital Design

    How to ensure the validity of the output in a design by a signal? How exactly the validity concept works? For example: In a design after so many clock pulses the output settles to a final value and how can we say that is stable and valid output signal for the given input?
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    Level converting flip flop

    What is a level converting flip-flop and its operation?
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    Verilog Code for zilog z80 microprocessor

    Hi, I wanted to know the verilog coding for zilog z80 microprocessor. Can anyone help me in this? Actually I want to write code for the entire microprocessor but I understood few blocks functioning, and rest of the blocks are very hard to understand.. I have attached the architecture of...
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