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Recent content by apalopohapa

  1. A

    Philosophical placement of counter in vhdl

    Hi. In vhdl, if a fsm needed to stay in a specific state for a specific number of clock cycles (for example, 1000), and you wanted to keep track of them using a counter, would you instantiate it within the fsm's architecture or somewhere else (e.g. the datapath) ? I ask because it doesn't feel...

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