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Recent content by anssprasad

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    Doubt regarding multicycle path setup and hold anlysis

    Hi, If the clocks are from the same source(when you say you are generating the 1MHz clock from 8 MHz then these two clocks should belong to the same domain) you need to set the 1MHz clock as a derived clock and define the corresponding parameters. When you do this the tool will automatically...
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    Help required for Design for Testability

    Hi Sudarshan When it comes to projects from the academic point of view I dont think what you do using a tool will add value. What you might be trying to find out is how the tool approaches a particular problem and how it can be improvised. For example take the PODEM algorithm for finding a test...
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    How to use a library without scan cell to insert scan chain?

    Re: How to use a library without scan cell to insert scan ch I think you also have a way of defining your own scan cells by instantiating the existing library modules.
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    Doubt regarding multicycle path setup and hold anlysis

    I think they should be defined as false paths, since they are clearly crossing clock domains.
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    why DFTAdvisor inserts back slash?

    Please upload the logfile and the output netlist if possible, I will take a look.
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    why DFTAdvisor inserts back slash?

    I think there are some settings that allow you to constrain the tool from renaming your ports. In general it does not do renaming. It is possible that there is another net or pin with the same name in the design post insertion. Please check.
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    Risks involved in having combos in Clock paths

    Hi Can anyone explain to me what could be the risks involved in having a mux in the clock path to select between two clocks? Thanks Prasad.
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    Synthesis library components question

    what is the difference between and clock AND cell and a normal AND cell in a technology library I mean how are the CK* cells different from their normal counterparts.
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    what does hookup polarity mean

    But we also have a "-active option" righ??
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    command in RC for adding a mux at the shared test input port

    define_dft what is the command to be used in RTL compiler to add a mux at the PI which, is used as a shared scan enable signal, with test_mode as its select _________________ Thanks Prasad
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    DFT Scan insertion query

    Hi, when doing DFT scan insertion which of the following is true or is a better approach: 1. Up to three additional pins are required to implement this type of scan. Only the SCAN ENABLE pin must be dedicated; the remainder of the pins(scan in, scan out) can be shared with primary inputs and...
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    what does hookup polarity mean

    Hi When defining DFT signals in Scan insertion using RC we use an option called hook up polarity. what does that mean. I am not clear from the explanation given in the Cadence manual. _________________ Thanks Prasad
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    Scan chain insertion with RC

    I got the following report when I used report dft_setup command in RC after scan chain insertion. test_mode: object name: h_resetn pin name: h_resetn hookup_pin: h_resetn hookup_polarity: non_inverted active: high ideal: false user defined: false My h_resetn signal is active low. I did not...
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    Using C for simulating LFSR and the LFSR code for cryptography or BIST

    Re: LFSR_application There should be no difference. It is used both in cryptography and BIST
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    Links to forums focused on synthesis

    Please give me links to dedicatied synthesis forums
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