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yes, they are mentioned in technology library.
For more info, look into the textbook "Static timing analysis for nanometer designs: a practical approach J. Bhasker, Rakesh Chadha".
Not sure about the chapter number, I think chapter-2 will clear your doubts.
hello,
I am in a problem of dealing with two shells, I have a some 10 lines of commands in a single file where the first 5 lines are only understood by tclsh and the next five lines are understood only by either my default bash or csh. if i source the file (containig tthese 10 commands), i...
I am not sure which constraints you are referring to.
It depends on which constraints you added/modified.
If more pessimistic constraints were used during synthesis and if they were relaxed in Tempus, the results are bounded.
If more optimistic constraints were used during synthesis, then a...
normally synthesis tools wont synthesize memories, if your design contains a memory block then you should keep srams blocks in the place of it. If those sram macro blocks are not available the you will black box or commented out in your RTL and perform synthesis. now the synthesis tool will...
yes, you should mention that command .
As per the process number , the tool will set the coupling capacitance threshold values accordingly in the background. design mode and analysis mode are to be set by us.
Hi sarfaraz,
you should not include library cell like that,
point 1: doing simulation on verilog /vhdl code is called functional simulation.
point 2: doing simulation on the netlist is called GTS (gate-level simulation).
I think you are trying to do point 2. first do the synthesis, synthesis...
The problem is that I don't know the correct format of these files so I don't know how to really edit these files and fix these units.
you can explore the chapter 3 (standard cell library) from the book: (STATIC TIMING ANALYSIS FOR NANAOMETER DESIGNS by jayaram bhaskar) to know much about the...
Hello all,
Is there any way of increasing the rated speed of the design , otherthan modifying the code.
i thought of physical constriants to constraint routing paths in fpga fabric which will alter the longer paths to smaller ones and hence increases the operating speed . (educate me, if im...
In my case, I am an RTL engineer with a exp of 1.8 years. Lets take my case of building a ASIP processor, the customer comes with an idea of implementing an algortihm. we simply understands the math behind the algorithm and will code mathematical instructions needed for that algorithm and if...
so, what should i do ? In the place/line of two-dimensional array declaration in the verilog code, i have to instantiate a particular sram cell so that my memory width, depth requirement and portlist(clka,clkb,dina,doutb,addra,addrb,we) of my memory design should match with the portlist of sram...
we don't have SRAM compiler tool, but sram libraries with the name temn28hpmhsram macros from imec via legal agreement in the past.
but how to make use of them, any genus commands or will genus automatically creates memories upon reading those sram macros.!!
I am very unclear on this.
Hi,
In which form this SRAM memory block available ?
how can i infer or instantiate in place of my ram . let it be " reg [7:0] ram [255:0] ; "?
give me the reference or example .
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