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Recent content by aniketd

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    How to make portable MACRO in Xilinx

    xilinx macro ncd nmc In Xilinx if i'm want to make my own macr i'll save .ncd as .nmc file but problem is that this MACRO is specific to that device which i have used I want to make it portable means i can use that .nmc file in other device also Does anyone know about this?????????
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    Does ASIC Design Engineer Required Good Knowlage of HDL

    Ya it's required I think it is the most essential thing (basic requirement of ASIC Engg.)
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    What is the best way to master VHDL

    hi, my suggestion is Practice a lot try to implement different designs by using any ISE evaluation version from Xilinx Practice only makes man Perfect !!!!!!!!!!!!!!!!!
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    VHDL Problem: declaration

    i think you don't have to include std under library header (there is no need to include work also) it's automatically included at the time of compilation can you elaborate your problem in detail
  5. A

    can a latch have setup and hold time violation...

    Latch Setup and Hold window appears on falling edge if it's high level sensitive latch or vice versa
  6. A

    Compare latch based and register based design

    latch register to tronix: There's a similar thread 'Moore vs Mealy design' in the same forum hvn similar discussion I don't think there is any co-relation between latch based design and register based design with STATE MACHINES what kind of similarity they have?????
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    Is it possible to do a complete latch based digital design for an ASIC ??

    Re: Latch based design can any one know about LSSD i.e Level Sensitive Scan Design??????
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    Is it possible to do a complete latch based digital design for an ASIC ??

    Re: Latch based design Companies proprietry tools are available for timing analysis but as they are proprietry they are not availabel to all and i don't think that any one have that information about that tools but it's critical to analyse asynchrnous circuit
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    Clock Divider in 8085

    is any one knows why clock divider is introduced in processor what is the need??? it's not possible to attatch that crystal
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    Is it possible to do a complete latch based digital design for an ASIC ??

    Re: Latch based design there are some companies working in this field but it's there proprietry design so it's not possible to mention as i don't know about it
  11. A

    Is it possible to do a complete latch based digital design for an ASIC ??

    Re: Latch based design ya it's possible to design a latch based digital circuit but from implementation point of view in FPGA or ASIC timing analysis may be critical
  12. A

    which language is easier?

    GO for C if you know C you can able to learn Verilog, Java...... easily but you should have enough knowledge of assembly also
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    Clock Divider in 8085

    is there any clock divider used in 8085 i think it's divide by 2 but i don't know why??? any one knows the answer
  14. A

    What's the relation between FPGA and ASIC?

    Re: Fpga and asic with FPGA it's fast to develope prototype where in case of ASIC development cycle is quite slow and Structured ASIC is combination of both
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    Inside Sparten-II??? (BSCAN, CAPTURE, STARTUP...)

    bscan capture what is the use of startup, bscan, capture blocks in SPARTAN-II FPGA?? (you can able to see those blocks from FPGA editor) how to use them??? any information???? as it is not mentioned in data sheet
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