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Hi All,
looking for a windows XP app.
Am after a 1cm x 1cm square that flashes between black and white. No boarders or anything just a plain square. flash rate around 0.5s.
If anyone can help or start me off with the code.
thanks
current output dac
Hi all,
ive recently come across current output DACs and i was wondering what they might be used in. The ones i have seen always seem to have a current to voltage converter which seems rather pointless if you could use a voltage output DAc in first place. Are there any...
hi all
i am sampling an input sine wave to my system using an A/D, i am then measuring using a scope the output from my D/A.
The problem i have is with a 1khz sine wave going in from my function generator the output looks distorted and does not look like the input signal.
Now i was aware i...
hi all
can someone double check my math here on this memory size problem.
i am storing sampled data into memory. the memory is 8M X16 bits.
i am not using all of this memory only from address 0 to 3FFFFF =(4194303)
now i am storing my data in memory unitl it is full. Using a stop watch i...
Re: sythesizable adder
Yeah FvM you are correct i am using offset binary, i forgot to mension that in an earlier post.
the data is coming on a databus, all 8 bits at a time. stored in a reg and then added together.
if i declar the reg as signed will it automaticaly change the MSB for me i.e...
Re: sythesizable adder
hi echo, thanks for the reply,
what about adding signed numbers. i know there is a signed statement in verilog that can be used but is it synthesizable?
basically i need to add two sets of numbers together. both are 8 bits. however i first need to convert the bits to...
hi all,
is it possible to use the "+" in verilog language and expect the compiler to make the logic for an adder.
e.g
input a;
input b;
output c;
assign c = a + b;
is code like this synthesizable or would i actually have to look at making an adder from logic gates etc.
thanks
hi all,
i keep getting an error message when i try to compile my verilog code.
it refers to a multi source. Now i can see where the error is occuring but i dont know how to fix it.
basically i have the outputs of 3 modules all connecting to the same input on another module.
e.g
output1...
spartan 3e verilog
you are correct with your pin assignments. If you use the provided reference manual it shows all the pin outs for all the peripherals the board contains.
Are you sure its the board and not your code? Have you simulated your code to see if it runs as you require?
As you have...
if i make a test bench and instantiate a top module i do not get any change in waveforms. They all stay to what they are initialised to.
my top module has three modules instantiated into it. Does that mean my test bench needs all three sub modules for it to work. i was under the impression...
Re: unexpected token
actually that was a typo in my haste to post the problem.
my code actually has it assigned as a 5 bit reg.
reg [4:0] count = 16;
always @ (posedge clk)
begin
if (start)
count = (count > 0) ? count-1 : count =16;
else
count = 16;
end
now call me stupid but i...
unexpected token
what is wrong with following code? i keep getting an unexpected token error message pointing to the condition statement, something to do with '=' ?????
reg count = 16;
always @ (posedge clk)
begin
if (start)
count = (count > 0) ? count-1 : count =16;
else
count = 16;
end
Re: memory
do all memory addresses start from zero or do they start from address one. Only the board i am using has 24 bit address but address zero has no connection acording to the user manual. therefore its a 23 bit address starting from 1 and going to 23.
Re: memory
thanks for the fast reply, i was wondering about the 23 addresses becasue one source says [22:0] and another says it is a 24 bit address but the extra bit must be for individual bits. Thanks
why do they describe the memory as 8m x 16, and 8m x 2 x 8 is still confussing?
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