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Recent content by anantha.bhat

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    schematic problem in formlity

    It would have helped if you are referring to RTL to Gate Equivalence checking or Gate to Gate .Indications are it is RTL2Gate. If so, first one could be a generic model of a sequential element derived from interpreting RTL code. Don't look for 1 to 1 correspondence between these pins. Is...
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    [TimingClosure] Pre- & Post- Placement Timing Optimization

    Please look at heading of this thread as "Timing Optimization without placement, and Timing optimization with placement." or "Differences in Optimization with and without placement". There are various substages in place and route. Global and detailed being two main flavors. Answer to your...
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    [TimingClosure] Pre- & Post- P&R logic synthesis

    Let us agree on Sub steps in various stages you mentioned... Synthesis: Translation followed by Optimization followed by Mapping Back end stage/work/group activities.. Placement, CTS, Routing, DRC/LVS & extraction. Timing/Area/Test/yield Optimizations and capping it with DRC/LVS & extraction...
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    [Synthesis] Hold violations in pre-layout synthesis

    "Hold violations" is too generic a word. Is it in port to 1st stage Reg? Reg2Reg? Reg2 constrained out port? Same clock domain or inter clock domain? Widely, hold violations are skew related. but as you can see it could just be constraints as well. Are they realistic... Plus, in realistic...
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    transform the .db lib into readable file

    Further to Oratie's comment, the reason is secrecy or IP protection, in a way. The very reason ASCII .lib file is converted to binary .db is to protect the numbers (which to a trained eye can reveal a lot on the process, etc). It is not normally acceptable to reverse this. Only RnD teams of...
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    Methods to reduce IR drop

    Many Physical design techniques are being discussed in this thread. But if you split I and R parts in IR analysis, avoiding huge rush of current due to simultaneously switching outputs (SSO) is a design approach. Reduce i(t). v(t) profile also changes. I believe, Apart from steady IR drop, ( if...
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    increase frequency vs define uncertainty

    Re: [Synthesis] increasing clock frequency vs adding clock uncertainty It is good to keep in mind that constraints play a role throughout design phase. So, it maynot be a good practice to just think of synthesis phase and resort to major modifications in later Physical implementation and Sign...
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